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Mbist Engineer Jobs (NOW HIRING)

Lead ASIC DFT Engineer Location: Remote Experience 10+ years of hands-on experience in ASIC Design ... Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon ...

Work on DFT lint checking, MBIST architecture, logic insertion, and scan insertion using industry ... Bachelors in Engineering and 8+ years of related experience or Masters degree and 6+ years of ...

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and ... This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST ...

Principal SoC DFT Engineer

San Jose, CA · On-site

$159K - $296K/yr

The Principal DFT Engineer will work on cutting-edge ASIC implementation for the Network ... MBIST and BISR * Boundary Scan (IEEE 1149.x) insertion * JTAG insertion and connectivity * High ...

ATPG and MBIST DFT patterns generation, bringup and debug * Yield Enhancement: Monitor wafer sort ... Cross functional: Work closely with Product Engineers and Test Engineers * Data Analytics ...

... Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for ... Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon ...

Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Below is the ... Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon ...

Opportunity for advancement DFT Engineer (Design for Test) Location: Santa Clara, CA (Onsite ... Develop and integrate Scan Compression, MBIST, LBIST, JTAG, and IJTAG solutions. * Perform ATPG ...

$140K - $150K/yr

DFT implementation (Scan, Compression, MBIST, LBIST, and Streaming Scan Network) from RTL to Post ... Work with Product Engineering team to bring up scan & mbist patterns on ATE. * Support silicon ...

DFT Engineer

Santa Clara, CA · On-site

$65 - $130/hr

Opportunity for advancement DFT Engineer (Design for Test) Location: Santa Clara, CA (Onsite ... Develop and integrate Scan Compression, MBIST, LBIST, JTAG, and IJTAG solutions. * Perform ATPG ...

Work on DFT lint checking, MBIST architecture, logic insertion, and scan insertion using industry ... Bachelors in Engineering and 8+ years of related experience or Masters degree and 6+ years of ...

Principal SoC DFT Engineer

San Jose, CA · On-site

$159K - $296K/yr

The Principal DFT Engineer will work on cutting-edge ASIC implementation for the Network ... MBIST and BISR * Boundary Scan (IEEE 1149.x) insertion * JTAG insertion and connectivity * High ...

ATPG and MBIST DFT patterns generation, bringup and debug * Yield Enhancement: Monitor wafer sort ... Cross functional: Work closely with Product Engineers and Test Engineers * Data Analytics ...

This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST ... Mentor DFT engineers and drive best practices Required Skills * 8+ years of hands-on ASIC DFT ...

DFT Engineer

Austin, TX · On-site

$106K - $184K/yr

The DFT Engineer delivers hands-on expertise in designing and deploying advanced Design-for-Test ... This role drives robust DFT architectures-including ATPG, MBIST, LBIST, and analog test solutions ...

Showing results 41-60

Mbist Engineer information

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$39K

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$137.5K

How much do mbist engineer jobs pay per year?

As of Sep 14, 2026, the average yearly pay for mbist engineer in the United States is $101,752.00, according to ZipRecruiter salary data. Most workers in this role earn between $84,000.00 and $116,500.00 per year, depending on experience, location, and employer.

What are popular job titles related to Mbist Engineer jobs?

For Mbist Engineer jobs, the most frequently searched job titles are:

Infographic showing various Mbist Engineer job openings in the United States as of August 2026, with employment types broken down into 94% Full Time, 2% Part Time, and 4% Contract. Highlights an 85% Physical, 5% Hybrid, and 10% Remote job distribution, with an average salary of $101,752 per year, or $48.9 per hour.

Senior Engineer - HBM Design for Test (DFT)

Richardson, TX • On-site

Micron Technology
Semiconductor and Electronic Component Manufacturing • 10K+ employees

Full-time

Medical, Dental, Vision, PTO

Re-posted 15 days ago


Key responsibilities

  • Define, implement, and document logic die MBIST architectures, including controller interaction, access mechanisms, sequencing, and broadcast behavior.

  • Own test definitions and DFT entry flows supporting MBIST, logic test, interface test, and debug use cases.

  • Support RTL debug and functional verification for DFT and MBIST features using Verilog and simulation tools.


Micron Technology rating

8.6

Company rating: 8.6 out of 10

Based on 43 frontline employees who took The Breakroom Quiz


Job description

Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
The Senior Engineer - HBM Design for Test (DFT) is a senior technical contributor responsible for defining, deploying, and sustaining best-in-class DFT solutions across HBM core die and base die spanning multiple HBM families with a primary focus on logic die MBIST support and architectural definitions along with implementation strategies.
This role emphasizes DFT architecture, specification ownership, multi-functional alignment, and program support, supported by strong technical expertise to ensure solutions are robust, scalable, and manufacturable. The role includes close partnership with DFT Verification to ensure feature completeness, coverage, and readiness for tape-out and silicon bring-up.
Key Responsibilities:
  • Ensure DFT solutions enable high-quality, low-cost, and manufacturable HBM products and define, implement, and document logic die MBIST architectures, including controller interaction, access mechanisms, sequencing, and broadcast behavior through high speed logic path design techniques.
  • Own test definitions and DFT entry flows supporting MBIST, logic test, interface test, and debug use cases including customer specified modes of operation.
  • Partner with logic and SoC architects to ensure DFT features are well-integrated, scalable, and generation-over-generation extensible
  • Support RTL debug and functional verification for DFT and MBIST related features through the use of Verilog and analog simulation tools.
  • Assist in defining checks, assertions, and coverage expectations related to logic die test functionality. Work with APR teams to support physical implementation of DFT and MBIST logic including:
    • Timing closure for test paths and control logic
    • Evaluation of clocking, reset, and scan/MBIST routing impacts
    • Review of congestion, power, and area tradeoffs related to DFT features
  • Provide guidance on DFT-friendly floorplanning and implementation practices, especially for high-fanout or broadcast test structures along with providing scripts to improve efficiency where applicable.
  • Support late-stage implementation and signoff debug related to DFT timing, connectivity, or integration issues
  • Serve as the DFT and MBIST point of contact for assigned programs or functional areas.. Using AI to improve job processes

Minimum Qualifications:
  • Bachelor's degree in Electrical Engineering or related field (Master's preferred)
  • 5+ years of experience in design-for-test, logic test, or related SoC/ASIC design roles
  • Strong understanding of MBIST fundamentals, memory architectures, and logic test concepts.
  • Working knowledge of memory architectures (HBM or DRAM preferred)
  • Experience influencing DFT requirements, specifications, and verification expectations

Preferred Qualifications:
  • Strong multi-functional collaboration skills, including work with verification organizations
  • Exposure to IEEE 1500 / DFT access mechanisms / broadcast test concepts
  • Experience supporting first silicon, qualification, or high-volume manufacturing debug
  • Clear written and verbal communication skill

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
To learn about your right to work click here.
To learn more about Micron, please visit micron.com/careers
For US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron's People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

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