DFT Engineer
Santa Clara, CA · On-site
The ideal candidate will have strong expertise in Design for Test (DFT) architecture, scan, MBIST, LBIST, JTAG, ATPG, and silicon debug. This is an excellent opportunity for a hands-on DFT Engineer ...
DFT Engineer
Santa Clara, CA · On-site
The ideal candidate will have strong expertise in Design for Test (DFT) architecture, scan, MBIST, LBIST, JTAG, ATPG, and silicon debug. This is an excellent opportunity for a hands-on DFT Engineer ...
$140K - $150K/yr
DFT implementation (Scan, Compression, MBIST, LBIST, and Streaming Scan Network) from RTL to Post ... Work with Product Engineering team to bring up scan & mbist patterns on ATE. * Support silicon ...
$140K - $150K/yr
DFT implementation (Scan, Compression, MBIST, LBIST, and Streaming Scan Network) from RTL to Post ... Work with Product Engineering team to bring up scan & mbist patterns on ATE. * Support silicon ...
DFT Engineers
Santa Clara, CA · On-site
MBIST Repair Implementation and Verification * Generating collaterals for Test Timing and Place and Route * Expertise in IJTAG 1687 standard and good at understanding ICL and PDL standard Spec
DFT Engineers
Santa Clara, CA · On-site
MBIST Repair Implementation and Verification * Generating collaterals for Test Timing and Place and Route * Expertise in IJTAG 1687 standard and good at understanding ICL and PDL standard Spec
DFT Engineer
San Jose, CA · On-site
ATPG and MBIST DFT patterns generation, bringup and debug * Yield Enhancement: Monitor wafer sort ... Cross functional: Work closely with Product Engineers and Test Engineers * Data Analytics ...
DFT Engineer
San Jose, CA · On-site
ATPG and MBIST DFT patterns generation, bringup and debug * Yield Enhancement: Monitor wafer sort ... Cross functional: Work closely with Product Engineers and Test Engineers * Data Analytics ...
DFT Engineer
San Jose, CA · On-site
DFT Engineer Location: San Jose CA, San Diego CA, Irvine CA, Chandler AZ (Onsite) Duration ... Experience in DFT flow, including architecture, IP integration (Test controllers, TAP, MBIST), and ...
Quick apply
DFT Engineer
San Jose, CA · On-site
DFT Engineer Location: San Jose CA, San Diego CA, Irvine CA, Chandler AZ (Onsite) Duration ... Experience in DFT flow, including architecture, IP integration (Test controllers, TAP, MBIST), and ...
Lead ASIC DFT engineer.
San Jose, CA · On-site
$194K/yr
Lead ASIC DFT Engineer Location: San Jose, CA Work Setup: Remote however once/month in office. PST ... This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST ...
Quick apply
Lead ASIC DFT engineer.
San Jose, CA · On-site
$194K/yr
Lead ASIC DFT Engineer Location: San Jose, CA Work Setup: Remote however once/month in office. PST ... This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST ...
DFT Engineer
Plano, TX · Remote
Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 8+ yrs to 15 yrs ... Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon ...
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DFT Engineer
Plano, TX · Remote
Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 8+ yrs to 15 yrs ... Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon ...
MBIST / BISR insertion and verification * Boundary Scan (IEEE 1149.x) * JTAG and HS Analog/mixed ... engineers to achieve first pass silicon success. Perform hands-on DFT implementation and ...
MBIST / BISR insertion and verification * Boundary Scan (IEEE 1149.x) * JTAG and HS Analog/mixed ... engineers to achieve first pass silicon success. Perform hands-on DFT implementation and ...
ASIC DFT Engineer
Irvine, CA · On-site
... Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for ... Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon ...
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ASIC DFT Engineer
Irvine, CA · On-site
... Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for ... Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon ...
ASIC DFT Engineer
Plano, TX · Remote
Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 8+ yrs to 15 yrs ... Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon ...
Quick apply
ASIC DFT Engineer
Plano, TX · Remote
Lead ASIC DFT Engineer Location: Remote, (Onsite) Duration: Contract Year of Exp: 8+ yrs to 15 yrs ... Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon ...
ASIC Engineer - Remote
Plano, TX · Remote
... Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for ... Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon ...
Quick apply
ASIC Engineer - Remote
Plano, TX · Remote
... Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for ... Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon ...
Lead ASIC DFT Engineer
San Jose, CA · On-site
Title - Lead ASIC DFT Engineer Location - San Jose, CA. Visa- USC/GC Experience: 10+ years of hands ... Own MBIST/LBIST integration, implementation, verification , and debug across design and silicon ...
Quick apply
Lead ASIC DFT Engineer
San Jose, CA · On-site
Title - Lead ASIC DFT Engineer Location - San Jose, CA. Visa- USC/GC Experience: 10+ years of hands ... Own MBIST/LBIST integration, implementation, verification , and debug across design and silicon ...
SoC DFT Engineer, Cloud
Sunnyvale, CA · On-site
$146K - $193K/yr
Experience with industry-standard test methodologies and platforms, such as ATE, MBIST, JTAG, or System Level Test (SLT). Preferred qualifications: * Master's degree or PhD in Electrical Engineering ...
SoC DFT Engineer, Cloud
Sunnyvale, CA · On-site
$146K - $193K/yr
Experience with industry-standard test methodologies and platforms, such as ATE, MBIST, JTAG, or System Level Test (SLT). Preferred qualifications: * Master's degree or PhD in Electrical Engineering ...
DFx Verification Engineer
Santa Clara, CA · On-site
$158K/yr
DFx Verification Engineer Location: - Santa Clara, CA (Onsite) Exp Range: - 5-20 Years of ... MBIST / LBIST * Boundary Scan (JTAG) * Memory repair and redundancy * Low-power test scenarios
DFx Verification Engineer
Santa Clara, CA · On-site
$158K/yr
DFx Verification Engineer Location: - Santa Clara, CA (Onsite) Exp Range: - 5-20 Years of ... MBIST / LBIST * Boundary Scan (JTAG) * Memory repair and redundancy * Low-power test scenarios
We are looking for a highly hands-on engineer who will be responsible for DFT architecture and implementation, verification, ATPG, MBIST and silicon bring-up for complex high-performance chips ...
We are looking for a highly hands-on engineer who will be responsible for DFT architecture and implementation, verification, ATPG, MBIST and silicon bring-up for complex high-performance chips ...
Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Duration ... Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon ...
Quick apply
Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Duration ... Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon ...
SoC DFT Engineer, Cloud
Sunnyvale, CA · On-site
$144K - $191K/yr
Experience with industry-standard test methodologies and platforms, such as ATE, MBIST, JTAG, or System Level Test (SLT). Preferred qualifications: * Master's degree or PhD in Electrical Engineering ...
SoC DFT Engineer, Cloud
Sunnyvale, CA · On-site
$144K - $191K/yr
Experience with industry-standard test methodologies and platforms, such as ATE, MBIST, JTAG, or System Level Test (SLT). Preferred qualifications: * Master's degree or PhD in Electrical Engineering ...
Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon ... Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and ...
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Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon ... Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and ...
... Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for ... Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon ...
... Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for ... Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon ...
DFT Engineer
Santa Clara, CA · On-site
Design for Test (DFT) Engineer Location: Hybrid (Travel to Santa Clara) Duration: 1year Key Skills ... Experience with MBIST (Memory Built-In Self-Test), including memory test architecture ...
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DFT Engineer
Santa Clara, CA · On-site
Design for Test (DFT) Engineer Location: Hybrid (Travel to Santa Clara) Duration: 1year Key Skills ... Experience with MBIST (Memory Built-In Self-Test), including memory test architecture ...
Mbist Engineer information
See salary details
$39K - $48K
3% of jobs
$48K - $56.9K
3% of jobs
$56.9K - $65.9K
4% of jobs
$65.9K - $74.8K
7% of jobs
$74.8K - $83.8K
6% of jobs
$84.5K is the 25th percentile. Wages below this are outliers.
$83.8K - $92.7K
6% of jobs
The median wage is $100.8K / yr.
$92.7K - $101.7K
21% of jobs
$101.7K - $110.6K
4% of jobs
$116.4K is the 75th percentile. Wages above this are outliers.
$110.6K - $119.6K
29% of jobs
$119.6K - $128.5K
2% of jobs
$128.5K - $137.5K
13% of jobs
$39K
$101.8K
$137.5K
How much do mbist engineer jobs pay per year?
As of Sep 14, 2026, the average yearly pay for mbist engineer in the United States is $101,752.00, according to ZipRecruiter salary data. Most workers in this role earn between $84,000.00 and $116,500.00 per year, depending on experience, location, and employer.
What are popular job titles related to Mbist Engineer jobs?
For Mbist Engineer jobs, the most frequently searched job titles are:
Job description
Job Title: DFT Engineer
Location: Santa Clara, CA
Work Arrangement: Onsite
Experience: 5+ Years
JOB DESCRIPTION
We are seeking an experienced DFT Engineer to join a cutting-edge Silicon Engineering team working on next-generation GPU and AI products. The ideal candidate will have strong expertise in Design for Test (DFT) architecture, scan, MBIST, LBIST, JTAG, ATPG, and silicon debug.
This is an excellent opportunity for a hands-on DFT Engineer to contribute to complex ASIC/SoC designs and next-generation semiconductor products.
KEY RESPONSIBILITIES
* Design and implement DFT architectures for complex ASIC/SoC designs.
* Develop and integrate Scan Compression, MBIST, LBIST, JTAG, and IJTAG solutions.
* Develop and execute ATPG patterns and perform fault simulation and test coverage analysis.
* Analyze and improve test coverage, test quality, and DFT implementation.
* Support silicon bring-up, post-silicon debug, failure analysis, and production test activities.
* Work closely with Design, Verification, Physical Design, Product Engineering, and other cross-functional teams.
* Participate in DFT implementation, verification, and signoff activities.
* Debug DFT-related issues across pre-silicon and post-silicon environments.
* Contribute to DFT methodologies, automation, and process improvements.
* Support the transition of DFT solutions from design through silicon validation and production.
REQUIRED QUALIFICATIONS
* 5+ years of hands-on experience in DFT engineering.
* Strong understanding of DFT architecture and methodologies for ASIC/SoC designs.
* Strong hands-on experience with:
* Scan
* Scan Compression
* MBIST
* LBIST
* ATPG
* JTAG
* IJTAG
* Strong knowledge of IEEE 1149.1, IEEE 1500, and IEEE 1687 standards.
* Experience with fault simulation and test coverage analysis.
* Proficiency in Verilog and/or SystemVerilog.
* Strong scripting/programming skills using Python, Perl, TCL, and/or Shell.
* Experience with one or more industry-standard DFT tools, such as:
* Synopsys TestMAX
* Synopsys DFT Compiler
* Siemens Tessent
* Cadence Modus
PREFERRED QUALIFICATIONS
* Experience with complex ASIC/SoC design environments.
* Experience working on GPU, AI, CPU, or other high-performance silicon products.
* Strong silicon bring-up and post-silicon debug experience.
* Experience with production test and test engineering methodologies.
* Experience collaborating across Design, Verification, Physical Design, and Product Engineering teams.
* Strong problem-solving and communication skills.