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Mask Layout Jobs in California (NOW HIRING)

Micron Technology

Senior Layout Designer

San Jose, CA · On-site

$86.10 - $165.31/hr

Layout/Mask Designer E2 - Layout/Mask Designer E3 Relocation Level: TBD Compensation The US base salary range that Micron Technology estimates it could pay for this full-time position is: $62.50 ...

Apple

RFIC Layout Engineer

Irvine, CA

$137K - $250K/yr

Detailed transistor-level layout of RF and analog circuit blocks, including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO. Preferred ...

Apple

RFIC Layout Engineer

Irvine, CA

$43.07 - $76.64/hr

Detailed transistor-level layout of RF and analog circuit blocks, including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO. Preferred ...

Apple

RFIC Layout Engineer

Irvine, CA

$137K - $250K/yr

Detailed transistor-level layout of RF and analog circuit blocks, including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO. Preferred ...

Apple

RFIC Layout Engineer

Irvine, CA

$137K - $250K/yr

Detailed transistor-level layout of RF and analog circuit blocks, including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO. Preferred ...

Apple

RFIC Layout Engineer

Irvine, CA

$43.07 - $76.64/hr

Detailed transistor-level layout of RF and analog circuit blocks, including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO. Preferred ...

Apple

RFIC Layout Engineer

Irvine, CA

$43.07 - $76.64/hr

Detailed transistor-level layout of RF and analog circuit blocks, including LNA, mixers, PLL, LO generation, modulators, power amplifiers, ADC/DAC, baseband filters, and bandgap/bias/LDO. Preferred ...

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All JobsMask Layout JobsMask Layout Jobs in California

Mask Layout information

See California salary details

$17

$19

$21

How much do mask layout jobs pay per hour?

As of Sep 2, 2026, the average hourly pay for mask layout in California is $19.93, according to ZipRecruiter salary data. Most workers in this role earn between $18.99 and $20.87 per hour, depending on experience, location, and employer.

What is a mask layout engineer?

Mask Layout engineers, also known as layout designers, are professionals who create the detailed layouts for integrated circuits (ICs) used in semiconductor manufacturing. They translate circuit schematics into precise geometric patterns that define where components like transistors and wires will be placed on a silicon wafer. This process is critical in ensuring that the final chip functions as intended and meets performance, area, and manufacturing requirements. Mask Layout engineers work closely with circuit designers and fabrication teams to optimize layouts for manufacturability, performance, and reliability.

What are the key skills and qualifications needed to thrive as a mask layout engineer?

To thrive as a Mask Layout Engineer, you need strong knowledge of semiconductor physics, IC design principles, and a relevant engineering degree. Proficiency with Electronic Design Automation (EDA) tools such as Cadence Virtuoso or Mentor Graphics, and understanding of DRC and LVS checks, is typically required. Attention to detail, problem-solving abilities, and effective teamwork are crucial soft skills in this role. These skills ensure accurate, efficient, and manufacturable chip layouts, directly impacting product quality and time to market.

What are some common challenges faced by mask layout engineers when working with cross-functional teams?

Mask Layout Engineers often collaborate closely with circuit designers, process engineers, and verification teams. A common challenge is aligning layout requirements with circuit specifications while adhering to foundry design rules and timelines. Effective communication and proactive issue resolution are crucial to ensure design intent is maintained and potential manufacturability or yield issues are identified early. Mask Layout Engineers also need to manage feedback from multiple stakeholders, which requires strong organizational and interpersonal skills.

What is the difference between Mask Layout vs Photomask Designer?

AspectMask LayoutPhotomask Designer
Primary RoleDesigns the geometric patterns for semiconductor masks at the layout level.Creates detailed photomask patterns based on circuit designs, focusing on manufacturability.
Skills & CertificationsVLSI design, CAD tools, semiconductor process knowledgeCAD software proficiency, semiconductor fabrication understanding
Work EnvironmentEDA tool environments, cleanroom facilities, design teamsDesign labs, manufacturing facilities, collaboration with fabrication teams
Industry UsageUsed in semiconductor chip design and fabricationUsed in photomask manufacturing for chip production

Mask Layout involves creating the geometric patterns for semiconductor masks, focusing on circuit design and layout optimization. Photomask Designer specializes in translating these designs into detailed photomask patterns for manufacturing. While both roles require similar technical skills and work environments, Mask Layout is more design-oriented, whereas Photomask Designer emphasizes pattern accuracy for fabrication.

What are popular job titles related to Mask Layout jobs in California?

For Mask Layout jobs in California, the most frequently searched job titles are:

What job categories do people searching Mask Layout jobs in California look for?

The top searched job categories for Mask Layout jobs in California are:

What cities in California are hiring for Mask Layout jobs?

Cities in California with the most Mask Layout job openings:

Mask Layout jobs near you
Infographic showing various Mask Layout job openings in California as of August 2026, with employment types broken down into 80% Full Time, and 20% Contract. Highlights an 100% In-person job distribution, with an average salary of $41,449 per year, or $19.9 per hour.

Layout (FIRE) Extraction Engineer

PDF Solutions, Inc.

Milpitas, CA • On-site

$120 - $160/hr

Other

Posted yesterday

New

Job description

Overview

PDF is seeking an experienced Layout (FIRE) Extraction Engineer to join the DFI team, who is responsible for Apps Support. The Layout (FIRE) Extraction Engineer is an organized and highly motivated team player with strong initiative and communication skills and possesses the drive to deliver quality results on time in a dynamic, multi-disciplined, intensive and highly productive small team environment.

Responsibilities
  1. Running Layout (FIRE) Extraction on client site to support onsite inspection application development.
  2. Remote support Layout (FIRE) Extraction for the R&D and Demo Application development in PDF Milpitas lab.
Qualifications

Bachelor’s Degree or higher in electrical engineering. Degrees, such as statistics or IT-related discipline may work, depending on work experience.

Skill Set
  • Core Technology & Knowledge
    • Theoretical and practical experience in OPC/RET (Resolution Enhancement Technology)
    • Comprehensive understanding of CMOS process flow
    • Knowledge of mask fabrication and design rules (DRC)
  • Software/Tool Proficiency
    • Experience with OPC/Mask simulation tools:
    • Mentor Graphics Calibre OPC/ILT
    • Synopsys Sentaurus/Litho
    • ASML Brion Tachyon
    • Layout processing tools:
    • Cadence, Synopsys, or KLayout
    • Scripting & Programming:
    • Hands‑on experience with Linux
    • Python, Perl, Tcl, Shell scripting
    • …
    • Experience in large-scale data processing and automation
  • Algorithm & Data Processing Skills
    • Understanding of pattern matching, shape transformation, and data optimization
    • Experience in OPC optimization using Machine Learning / AI (preferred)
  • Analytical & Problem-Solving Skills
    • Analysis and improvement of discrepancies between layout and actual pattern
    • Experience analyzing SEM/E-beam inspection data
    • Experience optimizing process window (PW) and depth of focus (DOF)
  • Collaboration & Work Skills
    • Experience collaborating with Design, Lithography, and Fab Process teams
    • Experience modifying and optimizing designs based on customer/internal feedback
    • Ability to read and understand English technical papers/datasheets and write reports
Pay Range

USD $120,000.00 - USD $160,000.00 /Yr.

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