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Mask Layout Design Engineer Jobs (NOW HIRING)

Senior Mask Layout Engineer

Bothell, WA ยท On-site

$126K - $166K/yr

As a Senior Mask Layout Engineer, you'll be part of a cross-functional team whose mission is to ... You will also have the opportunity to work closely with the photonic and ion trap design and ...

The team has an exciting opportunity for a IC Layout Design Engineer V to join our diverse team executing full-custom integrated circuit development with specific responsibility for driving the ...

As a Mask Layout Designer, you will have the opportunity to work with a team of layout designers, and design, process integration, and package engineers developing high quality Power MOSFETS for ...

As an AMR Layout Design Engineer will be responsible for the engineering design and deployment of AMR systems at customer facilities, validating and ensuring the systems as installed are safe and in ...

Analog Layout Design Engineer

Arizona, LA ยท On-site +1

$193K/yr

Analog Layout Design Engineer (Contract Position) Location: Remote | Headquarters: Tempe, Arizona, USA Company: Alphacore Inc. About Us Alphacore Inc. is a fast-growing innovator in high-performance ...

Analog Layout Design Engineer

Tempe, AZ ยท On-site

$193K/yr

Analog Layout Design Engineer (Contract Position) Location: Remote | Headquarters: Tempe, Arizona, USA Company: Alphacore Inc. About Us Alphacore Inc. is a fast-growing innovator in high-performance ...

Substrate Layout Design Engineer

Saratoga, CA ยท On-site

$240K - $275K/yr

Position Overview We are seeking an experienced Substrate Layout Design Engineer to support the development of an advanced multi-die organic based flip chip module that integrates multiple dies in a ...

We are seeking an experienced Senior Analog/Mixed-Signal Layout Design Engineer to help develop the next generation of high-performance focal-plane array readout integrated circuits (ROICs). These ...

Good Understanding of deep sub-micron layout techniques and issues in CMOS process technology nodes ... Mask Design team lead for the client engagement - Interface with the Circuit Design team at Onsite ...

Seeking an experienced Analog Layout Design Engineer to work onsite in the Bay Area. Requirement/Must Have: * Minimum 15+ years of related experience with an associate degree. * Experience with ...

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Mask Layout Design Engineer information

See salary details

$45K

$120.8K

$185.5K

How much do mask layout design engineer jobs pay per year?

As of Jun 22, 2026, the average yearly pay for mask layout design engineer in the United States is $120,849.00, according to ZipRecruiter salary data. Most workers in this role earn between $90,000.00 and $144,000.00 per year, depending on experience, location, and employer.

What are Mask Layout Design Engineers?

Mask Layout Design Engineers are specialized professionals in the semiconductor industry who create detailed layouts for integrated circuits (ICs). They translate circuit schematics into geometric patterns that define where components and connections will be formed on a silicon wafer. Their work ensures that chips are manufacturable, reliable, and meet performance specifications. They work closely with circuit designers and use advanced electronic design automation (EDA) tools to optimize layouts for size, speed, and power efficiency.

What are some common challenges Mask Layout Design Engineers face when working on advanced semiconductor nodes?

Mask Layout Design Engineers working on advanced semiconductor nodes often encounter challenges such as managing extremely tight design rules, ensuring layout accuracy to avoid costly fabrication errors, and coordinating with circuit designers to optimize layouts for performance and yield. The increasing complexity of devices at smaller nodes requires careful attention to detail and effective use of electronic design automation (EDA) tools. Collaborating closely with cross-functional teams, including process engineers and verification specialists, is essential to address these challenges and deliver high-quality layouts on schedule.

What are the key skills and qualifications needed to thrive as a Mask Layout Design Engineer, and why are they important?

To thrive as a Mask Layout Design Engineer, you need a solid background in semiconductor physics, IC design principles, and proficiency with layout tools, usually supported by a degree in electrical engineering or a related field. Expertise in industry-standard EDA tools like Cadence Virtuoso or Synopsys, and familiarity with design rule checks (DRC) and LVS verification are typical technical requirements. Strong attention to detail, problem-solving skills, and effective communication are essential soft skills for collaborating with design and fabrication teams. These abilities are crucial for ensuring accurate and manufacturable integrated circuit layouts that meet performance, cost, and reliability standards.

What is the difference between Mask Layout Design Engineer vs IC Design Engineer?

AspectMask Layout Design EngineerIC Design Engineer
CredentialsTypically requires a degree in Electrical Engineering or MicroelectronicsTypically requires a degree in Electrical Engineering or Computer Engineering
Work EnvironmentWorks primarily in mask shops or cleanroom environments focusing on photomask designWorks in design teams, CAD tools, and simulation environments for integrated circuits
Industry UsageUsed mainly in semiconductor fabrication and mask manufacturingUsed across semiconductor, consumer electronics, and computing industries

While both roles require a background in microelectronics and similar technical skills, the Mask Layout Design Engineer specializes in designing photomasks used in chip fabrication, whereas the IC Design Engineer focuses on designing the integrated circuits themselves. Both roles are essential in the semiconductor industry but differ in their specific focus and work environment.

More about Mask Layout Design Engineer jobs
What are the most commonly searched types of Mask Layout Design Engineer jobs? The most popular types of Mask Layout Design Engineer jobs are:
Infographic showing various Mask Layout Design Engineer job openings in the United States as of June 2026, with employment types broken down into 99% Full Time, and 1% Part Time. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution, with an average salary of $120,849 per year, or $58.1 per hour.
Senior Mask Layout Engineer

Senior Mask Layout Engineer

IonQ

Bothell, WA โ€ข On-site

$126K - $166K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Posted 23 days ago


Job description

About IonQ:
IonQ, Inc. [NYSE: IONQ] is the world's leading quantum platform and merchant supplier - delivering integrated quantum solutions across computing, networking, sensing, and security. IonQ's newest generation of quantum computers, the IonQ Tempo, is the latest in a line of cutting-edge systems that have been helping customers and partners including Amazon Web Services, and AstraZeneca achieve 20x performance results and accelerate innovation in drug discovery, materials science, financial modeling, logistics, cybersecurity, and defense. In 2025, the company achieved 99.99% two-qubit gate fidelity, setting a world record in quantum computing performance.
Headquartered in College Park, Maryland, IonQ has operations in California, Colorado, Massachusetts, Tennessee, Washington, Italy, South Korea, Sweden, Switzerland, Canada, and the United Kingdom. Our quantum computing services are available through all major cloud providers, while we also meet the needs of networking and sensing customers across land, sea, air, and space. IonQ is making quantum platforms more accessible and impactful than ever before.
We are looking for a Senior Mask Layout Engineer on the Fab Tapeout and Validation Team. As a Senior Mask Layout Engineer, you'll be part of a cross-functional team whose mission is to lead IonQ on its journey to build the world's best quantum computers to solve the world's most complex problems.
In this role, you will be the owner of full-reticle tapeouts for use in trapped-ion quantum computers, which could include both photonic and analog electronic layers. In addition, you will help develop and maintain the internal PDK and circuit layout libraries, as well as write scripts to automate the layout of masks for tapeouts. You will also have the opportunity to work closely with the photonic and ion trap design and testing teams to help develop new and game-changing quantum technology to enable scalable quantum computing, memory, and networking.
Responsibilities:
  • Conduct Python-based layout for full-reticle tapeouts with commercial foundries
  • Develop and maintain internal component PCell and automated circuit layout libraries
  • Interface with designers, test engineers, packaging engineers, and foundry team to define layout rules and component designs
  • Implement physical verification checks of layouts, including DRC and LVS
  • Develop detailed documentation of tapeouts and lead layout reviews with other team members
  • Work with cross-functional teams to understand circuit requirements and make recommendations to improve design, layout, and test workflows

You'd be a good fit with:
  • Bachelor's degree in Photonics, Physics, Electrical Engineering, or related field, or equivalent practical experience
  • Knowledge of semiconductor manufacturing processes and techniques
  • Excellent programming and software skills, including development in an IDE, proficiency with version control software, shell scripting, and code documentation
  • 2+ years of experience with Python-based mask layout software packages such as Luceda IPKISS, GDSFactory, or Klayout

You'd be a great fit with:
  • M.S. or Ph.D. in Photonics, Physics, Electrical Engineering, or related field
  • 5+ years experience in generating layout files for complex semiconductor flows with custom elements, such as MEMS, integrated photonics, or superconducting circuits
  • Past ownership of full-reticle tapeouts with commercial foundries
  • Experience with commercial simulation, verification, and layout environments such as Synopsys, Cadence, and Ansys
  • Familiarity with photonic and/or analog electronic device principles including design, test, and fabrication
  • Proficiency in physical verification including DRC, LVS, and ERC
  • Experience with semiconductor and/or photonic workflows for tapeout with commercial foundries
  • Excellent verbal and written communication skills
  • A meticulous attention to detail and excellent track record of documenting requirements, implementation plan, and tracking progress
  • Ability to work independently, prioritizing tasks and managing time effectively in a deadline-oriented environment

Location: This role is hybrid/onsite in one either College Park, MD or Bothell, WA campuses.
Travel: Up to 10%
Job ID: 1303
The approximate base salary range for this position is $126,887 - $166,127. The total compensation package includes base, bonus, and equity.
Compensation will vary based on individual factors such as education, qualifications, and experience of the final candidate(s), specific office location, and calibration against relevant market data and internal team equity. Posted base salary figures are subject to change as new market data becomes available. Our benefits include comprehensive medical, dental, and vision plans, matching 401K, unlimited PTO and paid holidays, parental/adoption leave, legal insurance, and a home technology stipend. Details of participation in these benefit plans will be provided when a candidate receives an offer of employment.
At IonQ, we believe in fair treatment, access, opportunity, and advancement for all while striving to identify and eliminate barriers. We empower employees to thrive by fostering a culture of autonomy, productivity, and respect. We are dedicated to creating an environment where individuals can feel welcomed, respected, supported, and valued.
We are committed to equity and justice. We welcome different voices and viewpoints and do not discriminate on the basis of race, religion, ancestry, physical and/or mental disability, medical condition, genetic information, marital status, sex, gender, gender identity, gender expression, transgender status, age, sexual orientation, military or veteran status, or any other basis protected by law. We are proud to be an Equal Employment Opportunity employer.
US Technical Jobs. The position you are applying for will require access to technology that is subject to U.S. export control and government contract restrictions. Employment with IonQ is contingent on either verifying "U.S. Person" (e.g., U.S. citizen, U.S. national, U.S. permanent resident, or lawfully admitted into the U.S. as a refugee or granted asylum) status for export controls and government contracts work, obtaining any necessary license, and/or confirming the availability of a license exception under U.S. export controls. Please note that in the absence of confirming you are a U.S. Person for export control and government contracts work purposes, IonQ may choose not to apply for a license or decline to use a license exception (if available) for you to access export-controlled technology that may require authorization, and similarly, you may not qualify for government contracts work that requires U.S. Persons, and IonQ may decline to proceed with your application on those bases alone. Accordingly, we will have some additional questions regarding your immigration status that will be used for export control and compliance purposes, and the answers will be reviewed by compliance personnel to ensure compliance with federal law.
US Non-Technical Jobs. Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Accordingly, we will have some additional questions regarding your immigration status that will be used for export control and compliance purposes, and the answers will be reviewed by compliance personnel to ensure compliance with federal law.
If you are interested in being a part of our team and mission, we encourage you to apply!