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Mask Layout Design Engineer Jobs (NOW HIRING)

Superbeo

Analog Layout Design Engineer

Santa Clara, CA · On-site

$237K/yr

Job Title: Analog Layout Design Engineer Job location: Santa Clara, CA, 95054 Job Duration: 3 ... Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that ...

IonQ

Senior Mask Layout Engineer

Bothell, WA · On-site

$126K - $166K/yr

As a Senior Mask Layout Engineer, you'll be part of a cross-functional team whose mission is to ... You will also have the opportunity to work closely with the photonic and ion trap design and ...

IC Enable

IC Layout Design Engineer

Richardson, TX · Hybrid

The team has an exciting opportunity for a IC Layout Design Engineer V to join our diverse team executing full-custom integrated circuit development with specific responsibility for driving the ...

onsemi

CAD Layout Engineer

Scottsdale, AZ · On-site

As a Mask Layout Designer, you will have the opportunity to work with a team of layout designers, and design, process integration, and package engineers developing high quality Power MOSFETS for ...

GABLETEK

AMR Layout Design Engineer

Troy, MI · On-site

As an AMR Layout Design Engineer will be responsible for the engineering design and deployment of AMR systems at customer facilities, validating and ensuring the systems as installed are safe and in ...

Alphacore Inc

Analog Layout Design Engineer

Arizona, LA · On-site +1

$193K/yr

Analog Layout Design Engineer (Contract Position) Location: Remote | Headquarters: Tempe, Arizona, USA Company: Alphacore Inc. About Us Alphacore Inc. is a fast-growing innovator in high-performance ...

Alphacore Inc

Analog Layout Design Engineer

Tempe, AZ · On-site

$193K/yr

Analog Layout Design Engineer (Contract Position) Location: Remote | Headquarters: Tempe, Arizona, USA Company: Alphacore Inc. About Us Alphacore Inc. is a fast-growing innovator in high-performance ...

Eridu AI

Substrate Layout Design Engineer

Saratoga, CA · On-site

$240K - $275K/yr

Position Overview We are seeking an experienced Substrate Layout Design Engineer to support the development of an advanced multi-die organic based flip chip module that integrates multiple dies in a ...

Teledyne

Sr. ASIC Layout Design Engineer

Goleta, CA

$113K - $151K/yr

We are seeking an experienced Senior Analog/Mixed-Signal Layout Design Engineer to help develop the next generation of high-performance focal-plane array readout integrated circuits (ROICs). These ...

Stem Xpert

Mask Design Engineer

Hillsboro, OR · On-site

Good Understanding of deep sub-micron layout techniques and issues in CMOS process technology nodes ... Mask Design team lead for the client engagement - Interface with the Circuit Design team at Onsite ...

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All JobsMask Layout Design Engineer Jobs

Mask Layout Design Engineer information

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$45K

$120.8K

$185.5K

How much do mask layout design engineer jobs pay per year?

As of Jun 21, 2026, the average yearly pay for mask layout design engineer in the United States is $120,849.00, according to ZipRecruiter salary data. Most workers in this role earn between $90,000.00 and $144,000.00 per year, depending on experience, location, and employer.

What are Mask Layout Design Engineers?

Mask Layout Design Engineers are specialized professionals in the semiconductor industry who create detailed layouts for integrated circuits (ICs). They translate circuit schematics into geometric patterns that define where components and connections will be formed on a silicon wafer. Their work ensures that chips are manufacturable, reliable, and meet performance specifications. They work closely with circuit designers and use advanced electronic design automation (EDA) tools to optimize layouts for size, speed, and power efficiency.

What are some common challenges Mask Layout Design Engineers face when working on advanced semiconductor nodes?

Mask Layout Design Engineers working on advanced semiconductor nodes often encounter challenges such as managing extremely tight design rules, ensuring layout accuracy to avoid costly fabrication errors, and coordinating with circuit designers to optimize layouts for performance and yield. The increasing complexity of devices at smaller nodes requires careful attention to detail and effective use of electronic design automation (EDA) tools. Collaborating closely with cross-functional teams, including process engineers and verification specialists, is essential to address these challenges and deliver high-quality layouts on schedule.

What are the key skills and qualifications needed to thrive as a Mask Layout Design Engineer, and why are they important?

To thrive as a Mask Layout Design Engineer, you need a solid background in semiconductor physics, IC design principles, and proficiency with layout tools, usually supported by a degree in electrical engineering or a related field. Expertise in industry-standard EDA tools like Cadence Virtuoso or Synopsys, and familiarity with design rule checks (DRC) and LVS verification are typical technical requirements. Strong attention to detail, problem-solving skills, and effective communication are essential soft skills for collaborating with design and fabrication teams. These abilities are crucial for ensuring accurate and manufacturable integrated circuit layouts that meet performance, cost, and reliability standards.

What is the difference between Mask Layout Design Engineer vs IC Design Engineer?

AspectMask Layout Design EngineerIC Design Engineer
CredentialsTypically requires a degree in Electrical Engineering or MicroelectronicsTypically requires a degree in Electrical Engineering or Computer Engineering
Work EnvironmentWorks primarily in mask shops or cleanroom environments focusing on photomask designWorks in design teams, CAD tools, and simulation environments for integrated circuits
Industry UsageUsed mainly in semiconductor fabrication and mask manufacturingUsed across semiconductor, consumer electronics, and computing industries

While both roles require a background in microelectronics and similar technical skills, the Mask Layout Design Engineer specializes in designing photomasks used in chip fabrication, whereas the IC Design Engineer focuses on designing the integrated circuits themselves. Both roles are essential in the semiconductor industry but differ in their specific focus and work environment.

More about Mask Layout Design Engineer jobs
What are the most commonly searched types of Mask Layout Design Engineer jobs? The most popular types of Mask Layout Design Engineer jobs are:
What job categories do people searching Mask Layout Design Engineer jobs look for? The top searched job categories for Mask Layout Design Engineer jobs are:
Mask Layout Design Engineer jobs near you
Infographic showing various Mask Layout Design Engineer job openings in the United States as of June 2026, with employment types broken down into 99% Full Time, and 1% Part Time. Highlights an 87% Physical, 5% Hybrid, and 8% Remote job distribution, with an average salary of $120,849 per year, or $58.1 per hour.

Analog Layout Design Engineer

Superbeo

Santa Clara, CA • On-site

$237K/yr

Contractor

Posted 15 days ago

Job description

Job Title: Analog Layout Design Engineer
Job location: Santa Clara, CA, 95054
Job Duration: 3 Months, Contract to Hire
Job Description:
  • Experience with layout of cutting-edge high-performance, high-speed CMOS integrated circuits in older foundry CMOS process nodes in 40nm, 55nm, 65nm and 130nm following best practices from the industry.
  • Reviewing and analyzing floorplans and complex circuits with circuit designers
  • Running complete set of design verification tools available on AMS blocks
  • Interpreting LVS, DRC and ERC reports to find the fastest way to complete layout
  • Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that meet stringent matching performance, area, and power requirements
  • Be a great role model, by inspiring and motivating team, and Establishing Effective Organizational Structure and Communication Protocols. Able to Delegate and Empower team along with Effective Time Management.
  • Working with the circuit designer or Layout-Lead to plan/schedule work and negotiate any layout trade-offs as needed
Qualifications:
  • 10+ years of experience in analog/mixed-signal layout design of deep submicron CMOS circuits and at least 3+ years of recent experience on advance nodes including FinFET technologies
  • Experience with and knowledge of analog/mixed-signal IP (e.g., SERDES PHY, transmitter and receiver, PLL, DDR PHY, ADCs, DACs, LDOs, etc.)
  • Experience leading complex layout macros during the full design cycle from floorplan analysis to completion of physical design verification
  • Great understanding of CAD flows and tools related to analog/mixed-signal layout design
  • Experience crafting well-matched, low noise, and low power analog blocks consisting of transistors, resistors, capacitors, pad IO's, ESD structures, etc.
  • High level of proficiency in custom, as well as standard cell-based, floorplanning and hierarchical layout assembly
  • Must understand issues of IR drop, RC delay, electro-migration, self-heating and coupling capacitance
  • Must recognize failure prone circuit and layout structures, have experience with analog and DFM standard methodologies, and enthusiastically work with circuit designer or layout lead for the best approach to problems
  • High level of proficiency in interpretation of CALIBRE DRC, ERC, LVS, etc., reports
  • Knowledge of CADENCE or MENTOR GRAPHICS layout tools.
  • Excellent interpersonal skills and able to work with remote teams
  • Synopsys/Cadence/Mentor Layout tools (Preference: 5)
  • Python (Preference: 3)
  • TSMC 7nm or 5nm (Preference: 3)
  • TSMC 3nm (Preference: 5)