We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and dynamic group of diverse individuals responsible for contributing to our latest generation ...
We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and dynamic group of diverse individuals responsible for contributing to our latest generation ...
Are you a Mask Layout Design Engineer who is seeking an outstanding opportunity? We are looking for a Senior Mask Layout Design Engineer - someone who is excited to join a growing group of diverse ...
Are you a Mask Layout Design Engineer who is seeking an outstanding opportunity? We are looking for a Senior Mask Layout Design Engineer - someone who is excited to join a growing group of diverse ...
Are you a Mask Layout Design Engineer who is seeking an outstanding opportunity? We are looking for a Senior Mask Layout Design Engineer - someone who is excited to join a growing group of diverse ...
Are you a Mask Layout Design Engineer who is seeking an outstanding opportunity? We are looking for a Senior Mask Layout Design Engineer - someone who is excited to join a growing group of diverse ...
Analog Layout Design Engineer
Santa Clara, CA · On-site
$237K/yr
Analog Layout Design Engineer Job Location: Santa Clara, CA (Onsite for 5 days a week) Job Type ... Experience in industry standard mask design/verification tools (Cadence/Synopsys, Calibre ) * Hands ...
Quick apply
Analog Layout Design Engineer
Santa Clara, CA · On-site
$237K/yr
Analog Layout Design Engineer Job Location: Santa Clara, CA (Onsite for 5 days a week) Job Type ... Experience in industry standard mask design/verification tools (Cadence/Synopsys, Calibre ) * Hands ...
Design Integration Engineer (49386)
Milpitas, CA · On-site
$92K - $136K/yr
Tracks wafer schedules, mask manufacturing progress in the fab, and vendor interactions to ensure just-in-time delivery of masks, tools, or wafers * Updates, creates, and maintains CAD libraries for ...
Design Integration Engineer (49386)
Milpitas, CA · On-site
$92K - $136K/yr
Tracks wafer schedules, mask manufacturing progress in the fab, and vendor interactions to ensure just-in-time delivery of masks, tools, or wafers * Updates, creates, and maintains CAD libraries for ...
Design Integration Engineer (49386)
$118K - $159K/yr
Tracks wafer schedules, mask manufacturing progress in the fab, and vendor interactions to ensure just-in-time delivery of masks, tools, or wafers * Updates, creates, and maintains CAD libraries for ...
Design Integration Engineer (49386)
$118K - $159K/yr
Tracks wafer schedules, mask manufacturing progress in the fab, and vendor interactions to ensure just-in-time delivery of masks, tools, or wafers * Updates, creates, and maintains CAD libraries for ...
All tasks related to mask design and layout of photonic integrated circuits * Creating mask designs in conjunction with optical designers and process engineers. * Creating design rules and ...
All tasks related to mask design and layout of photonic integrated circuits * Creating mask designs in conjunction with optical designers and process engineers. * Creating design rules and ...
Job Title: Analog Layout Design Engineer Job location: Santa Clara, CA, 95054 Job Duration: 3 ... Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that ...
Quick apply
Job Title: Analog Layout Design Engineer Job location: Santa Clara, CA, 95054 Job Duration: 3 ... Utilizing advanced CAD tools and mask design knowledge to deliver correct and robust layout that ...
RF/Analog Mixed Signal Design Engineer
$129K - $225K/yr
Drive mask design to implement layout views of designs and drive layout reviews. Run post-layout ... Experience in working with production test engineers to produce test plans and design for ...
RF/Analog Mixed Signal Design Engineer
$129K - $225K/yr
Drive mask design to implement layout views of designs and drive layout reviews. Run post-layout ... Experience in working with production test engineers to produce test plans and design for ...
Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...
Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...
PLL Design Engineer
$129K - $225K/yr
We are seeking a highly skilled PLL Design Engineer to join our engineering team. The ideal ... Working closely with the mask design team to implement layout views of designs. Preferred ...
PLL Design Engineer
$129K - $225K/yr
We are seeking a highly skilled PLL Design Engineer to join our engineering team. The ideal ... Working closely with the mask design team to implement layout views of designs. Preferred ...
PLL Design Engineer
$184K - $324K/yr
We are seeking a highly skilled PLL Design Engineer to join our engineering team. The ideal ... Working closely with the mask design team to implement layout views of designs. Preferred ...
PLL Design Engineer
$184K - $324K/yr
We are seeking a highly skilled PLL Design Engineer to join our engineering team. The ideal ... Working closely with the mask design team to implement layout views of designs. Preferred ...
RF/Analog Mixed Signal Design Engineer
$184K - $324K/yr
Drive mask design to implement layout views of designs and drive layout reviews. Run post-layout ... Experience in working with production test engineers to produce test plans and design for ...
RF/Analog Mixed Signal Design Engineer
$184K - $324K/yr
Drive mask design to implement layout views of designs and drive layout reviews. Run post-layout ... Experience in working with production test engineers to produce test plans and design for ...
Analog IC Design Engineer, High-Speed
Mountain View, CA · On-site
$238K/yr
As a member of the analog team, you'll collaborate with our architects and engineers to develop ... Drive block-level floorplan, mask design views, and their reviews * Run post-layout and mixed ...
Analog IC Design Engineer, High-Speed
Mountain View, CA · On-site
$238K/yr
As a member of the analog team, you'll collaborate with our architects and engineers to develop ... Drive block-level floorplan, mask design views, and their reviews * Run post-layout and mixed ...
Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...
Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...
ROIC Design Engineer Principal
Goleta, CA · On-site
... mask design • Serial interface designs including serial peripheral, I2C, and other standard ... of engineering teams over product lifecycles • Understanding of IR sensor systems and all of ...
ROIC Design Engineer Principal
Goleta, CA · On-site
... mask design • Serial interface designs including serial peripheral, I2C, and other standard ... of engineering teams over product lifecycles • Understanding of IR sensor systems and all of ...
Analog Circuit Design Engineer
Cupertino, CA · On-site
$249K/yr
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... Minimum Qualifications Bachelor's of Science in Electric Engineering with 10+ years of relevant ...
Analog Circuit Design Engineer
Cupertino, CA · On-site
$249K/yr
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... Minimum Qualifications Bachelor's of Science in Electric Engineering with 10+ years of relevant ...
Analog IC Design Engineer
Cupertino, CA · On-site
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... Minimum Qualifications Bachelor's of Science in Electric Engineering Required. Preferred ...
Analog IC Design Engineer
Cupertino, CA · On-site
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... Minimum Qualifications Bachelor's of Science in Electric Engineering Required. Preferred ...
Analog IC Design Engineer
Cupertino, CA · On-site
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... Minimum Qualifications Bachelor's of Science in Electric Engineering with 10+ years of relevant ...
Analog IC Design Engineer
Cupertino, CA · On-site
Drive mask design to implement layout view of designs. Top-level simulations to validate top-level ... Minimum Qualifications Bachelor's of Science in Electric Engineering with 10+ years of relevant ...
Wireless Design Engineer
San Diego, CA · On-site
As a Wireless Design Engineer, you will be responsible for RTL design of wireless MAC and its interface with the rest of the wireless SoC. You will interact with the software team, wireless system ...
Wireless Design Engineer
San Diego, CA · On-site
As a Wireless Design Engineer, you will be responsible for RTL design of wireless MAC and its interface with the rest of the wireless SoC. You will interact with the software team, wireless system ...
Mask Design Engineer information
See California salary details
$44.4K - $57K
4% of jobs
$57K - $69.6K
2% of jobs
$69.6K - $82.2K
12% of jobs
$92.5K is the 25th percentile. Wages below this are outliers.
$82.2K - $94.8K
9% of jobs
$94.8K - $107.4K
11% of jobs
The median wage is $119.1K / yr.
$107.4K - $120K
14% of jobs
$120K - $132.6K
22% of jobs
$135K is the 75th percentile. Wages above this are outliers.
$132.6K - $145.3K
9% of jobs
$145.3K - $157.9K
9% of jobs
$157.9K - $170.5K
3% of jobs
$170.5K - $183.1K
6% of jobs
$44.4K
$119.3K
$183.1K
How much do mask design engineer jobs pay per year?
What is a mask design engineer?
What are some common challenges faced by Mask Design Engineers during the IC layout process?
What is the difference between Mask Design Engineer vs Photomask Fabrication Engineer?
| Aspect | Mask Design Engineer | Photomask Fabrication Engineer |
|---|---|---|
| Primary Role | Designs photomasks used in semiconductor manufacturing | Manufactures and inspects photomasks based on design specifications |
| Skills & Certifications | Knowledge of CAD tools, semiconductor processes, optical design | Experience with lithography, cleanroom protocols, quality control |
| Work Environment | Design labs, CAD rooms, collaboration with chip designers | Cleanrooms, fabrication facilities, equipment operation |
| Industry Usage | Used in semiconductor and electronics manufacturing | Used in photomask production for chip fabrication |
While both roles are essential in semiconductor manufacturing, the Mask Design Engineer focuses on creating the design files for photomasks, whereas the Photomask Fabrication Engineer handles the physical production and quality control of these masks. Both positions require specialized skills and work closely within the same industry but serve different stages of the mask creation process.
What are the key skills and qualifications needed to thrive as a Mask Design Engineer, and why are they important?
What are Mask Design Engineers?
How much does a mask design engineer make at Nvidia?
What is the highest paid design job?
What's a design engineer's salary?
Job description
NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. More recently, GPU deep learning ignited modern AI - the next era of computing. NVIDIA is a "learning machine" that constantly evolves by adapting to new opportunities that are hard to take on, that only we can pursue, and that matter to the world. This is our life's work, to amplify human creativity and intelligence. We would love to hear from you!
We are looking for a Senior Mask Layout Design Engineer, someone who is excited to join a growing and dynamic group of diverse individuals responsible for contributing to our latest generation chiplet interface projects
What you'll be doing:
Performing physical layout for mixed-signal functions like top level, high speed datapaths and high-speed clocking designs in state-of-the-art sub-micron CMOS technologies using Cadence tools.
You'll work closely with mixed-signal design engineers to customize designs for integration in VLSI products.
Take part in floor planning, custom layout and verifying against design rules and schematics.
What we need to see:
Have a BSEE or equivalent experience.
Minimum of 8+ years industry experience in Mask and Layout Design.
Working independently on creating layout with excellent quality
Deep understanding and previous experience for FinFET technology is a must
You are an authority with Cadence custom circuit design tools - particularly virtuoso.
Able to handle fast-paced project and iterate quickly based on designer's feedback
You can work effectively in a team, good interpersonal skills, enthusiasm, and positive energy.
Scripting languages like perl, python, skill etc.is a plus
Should have knowledge of DRC and LVS checking flows, ability to customize decks.
#LI-Hybrid
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 132,000 USD - 207,000 USD for Level 4, and 148,000 USD - 235,750 USD for Level 5.You will also be eligible for equity and benefits.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.About Nvidia
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1993