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Makefile Jobs (NOW HIRING)

millenniumsoft

Cloud SaaS Developer - Remote

San Diego, CA · On-site +1

$59.75 - $81.75/hr

Strong hands-on development expertise with Go, TypeScript, Makefile, JavaScript, Shell, HTML, and React. * Experience in designing and integrating RESTful APIs. * Must have good coding practices ...

Apple

CAD Engineer - PDV

Austin, TX

$147K - $272K/yr

... Makefile or C Experience with flow automation and development Minimum Qualifications Minimum requirement of BS + 3 years of relevant industry experience Pay & Benefits At Apple, base pay is one part ...

US Tech Solutions

Lead consultant

Santa Clara, CA

... Ant, Makefile, MSBuild Code Quality - SonarQube, Crucible, JUnit PMD, Checkstyle, Checkmarx Continuous Integration - Jenkins, Cruise Control, Bamboo, Teamcity Continuous Deployment - uDeploy ...

GlobalFoundries

Senior Engineer Emulation

Santa Clara, CA · On-site

$98K - $170K/yr

Strong scripting skills with Python, TCL, Bash, and Makefile * Strong debugging skills for issues including but not limited to: cpu-internal bugs, integration bugs, emulator configuration or ...

Apple

CAD Engineer - PDV

Austin, TX

$147K - $272K/yr

... Makefile or C Experience with flow automation and development Minimum Qualifications Minimum requirement of BS + 3 years of relevant industry experience Pay & Benefits At Apple, base pay is one part ...

Apple

CAD Engineer - PDV

Austin, TX · On-site

$171K - $302K/yr

... Makefile or C Experience with flow automation and development in advanced nodes. Rule coding in PERC is a plus. Knowledge of ML/LLM is a plus. Knowledge of parasitic extraction, SKILL coding, and PnR ...

Apple

CAD Engineer - PDV

Austin, TX · On-site

$171K - $302K/yr

... Makefile or C Experience with flow automation and development in advanced nodes. Rule coding in PERC is a plus. Knowledge of ML/LLM is a plus. Knowledge of parasitic extraction, SKILL coding, and PnR ...

Apple

CAD Engineer - PDV

Austin, TX

$171K - $302K/yr

... Makefile or C Experience with flow automation and development in advanced nodes. Rule coding in PERC is a plus. Knowledge of ML/LLM is a plus. Knowledge of parasitic extraction, SKILL coding, and PnR ...

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Makefile information

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How much do makefile jobs pay per hour?

As of Jun 19, 2026, the average hourly pay for makefile in the United States is $59.11, according to ZipRecruiter salary data. Most workers in this role earn between $48.32 and $69.23 per hour, depending on experience, location, and employer.

What is the difference between Makefile vs Build Automation Engineer?

AspectMakefileBuild Automation Engineer
Primary RoleDefines build instructions using Makefile scriptsDesigns and implements automated build systems and pipelines
Skills & CertificationsKnowledge of Make, scripting, basic programmingExperience with CI/CD tools, scripting, programming languages
Work EnvironmentSoftware development teams, primarily in development or DevOpsDevOps teams, software engineering, continuous integration environments
Industry UsageUsed by developers to automate compilation and build processesUsed by DevOps and build engineers to streamline deployment pipelines

While a Makefile is a specific file used to automate build tasks in software projects, a Build Automation Engineer is a professional responsible for designing and maintaining automated build systems. The Makefile is a tool within the broader scope of build automation, which is the core focus of a Build Automation Engineer.

More about Makefile jobs
What job categories do people searching Makefile jobs look for? The top searched job categories for Makefile jobs are:
Makefile jobs near you
Infographic showing various Makefile job openings in the United States as of June 2026, with employment types broken down into 90% Full Time, 2% Temporary, and 8% Contract. Highlights an 72% Physical, 23% Hybrid, and 5% Remote job distribution, with an average salary of $122,950 per year, or $59.1 per hour.
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

SpaceX

Austin, TX • On-site

Other

Posted 23 days ago

SpaceX rating

8.7

Company rating: 8.7 out of 10

Based on 144 frontline employees who took The Breakroom Quiz

13th of 60 rated aerospace companies

Job description

SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)

At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

  • Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
  • Develop/improve physical design methodologies and automation scripts for various implementation steps
  • Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
  • Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
  • Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

BASIC QUALIFICATIONS:

  • Bachelor's degree in electrical engineering, computer engineering or computer science
  • 5+ years of ASIC and/or physical design flow development experience in industry

PREFERRED SKILLS AND EXPERIENCE:

  • Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
  • Strong experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
  • Knowledge of deep sub-micron FinFET and CMOS solid state physics
  • Knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
  • Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
  • Familiar with CMOS analog circuit and physical design
  • Knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
  • Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
  • Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS:    

  • Ability to work extended hours and weekends as needed to meet critical project milestones   

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