SoC Platform Engineer
Saratoga, CA · On-site
... low-power SoC design and power intent methodologies (UPF/CPF). • Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Collaboration and ...
Saratoga, CA · On-site
... low-power SoC design and power intent methodologies (UPF/CPF). • Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Collaboration and ...
Saratoga, CA · On-site
... low-power SoC design and power intent methodologies (UPF/CPF). • Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Collaboration and ...
Santa Clara, CA · On-site
$250/hr
Master's Degree in Computer Engineering or Electrical Engineering (or equivalent experience) * Strong understanding of SoC architecture for low power mobile devices, including DVFS, power domains ...
Santa Clara, CA · On-site
$250/hr
Master's Degree in Computer Engineering or Electrical Engineering (or equivalent experience) * Strong understanding of SoC architecture for low power mobile devices, including DVFS, power domains ...
... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... performance, low power wireless SoCs. As a member of the team, you will work closely with SoC ...
... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... performance, low power wireless SoCs. As a member of the team, you will work closely with SoC ...
... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... performance, low power wireless SoCs. As a member of the team, you will work closely with SoC ...
... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... performance, low power wireless SoCs. As a member of the team, you will work closely with SoC ...
SoC Design Engineer Job Duties: Responsible for digital design and verification of image sensor and ... Design optimization techniques for area, power, and timing. * Using industry-standard digital ...
Quick apply
SoC Design Engineer Job Duties: Responsible for digital design and verification of image sensor and ... Design optimization techniques for area, power, and timing. * Using industry-standard digital ...
Santa Clara, CA · On-site
$156K - $160K/yr
Description Job Title: SoC Design Engineer Job Duties: Responsible for digital design and ... Design optimization techniques for area, power, and timing. * Using industry-standard digital ...
Santa Clara, CA · On-site
$156K - $160K/yr
Description Job Title: SoC Design Engineer Job Duties: Responsible for digital design and ... Design optimization techniques for area, power, and timing. * Using industry-standard digital ...
Santa Clara, CA · On-site
$156K - $160K/yr
SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Arithmetic circuit design, timing analysis; synchronous and asynchronous FSMs; power, test, and ...
Santa Clara, CA · On-site
$156K - $160K/yr
SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Arithmetic circuit design, timing analysis; synchronous and asynchronous FSMs; power, test, and ...
$122K - $214K/yr
... low-power driven architecture, and best-in-class DV methodology. You will gain knowledge on ... As a Design Verification Engineer on our team, you'll be at the center of the verification effort ...
$122K - $214K/yr
... low-power driven architecture, and best-in-class DV methodology. You will gain knowledge on ... As a Design Verification Engineer on our team, you'll be at the center of the verification effort ...
Santa Clara, CA · On-site
$156K - $160K/yr
SoC Design Engineer Job Duties: Responsible for digital design and verification of image sensor and ... Design optimization techniques for area, power, and timing. * Using industry-standard digital ...
Santa Clara, CA · On-site
$156K - $160K/yr
SoC Design Engineer Job Duties: Responsible for digital design and verification of image sensor and ... Design optimization techniques for area, power, and timing. * Using industry-standard digital ...
Santa Clara, CA · On-site
$156K - $160K/yr
SoC Design Engineer Job Duties: Responsible for digital design and verification of image sensor and ... Design optimization techniques for area, power, and timing. * Using industry-standard digital ...
Santa Clara, CA · On-site
$156K - $160K/yr
SoC Design Engineer Job Duties: Responsible for digital design and verification of image sensor and ... Design optimization techniques for area, power, and timing. * Using industry-standard digital ...
$122K - $214K/yr
... low-power driven architecture, and best-in-class DV methodology. You will gain knowledge on ... As a Design Verification Engineer on our team, you'll be at the center of the verification effort ...
$122K - $214K/yr
... low-power driven architecture, and best-in-class DV methodology. You will gain knowledge on ... As a Design Verification Engineer on our team, you'll be at the center of the verification effort ...
Santa Clara, CA · On-site
SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Arithmetic circuit design, timing analysis; synchronous and asynchronous FSMs; power, test, and ...
Quick apply
Santa Clara, CA · On-site
SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Arithmetic circuit design, timing analysis; synchronous and asynchronous FSMs; power, test, and ...
$122K - $214K/yr
... low-power driven architecture, and best-in-class DV methodology. You will gain knowledge on ... As a Design Verification Engineer on our team, you'll be at the center of the verification effort ...
$122K - $214K/yr
... low-power driven architecture, and best-in-class DV methodology. You will gain knowledge on ... As a Design Verification Engineer on our team, you'll be at the center of the verification effort ...
Santa Clara, CA · On-site
$156K - $160K/yr
SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Arithmetic circuit design, timing analysis; synchronous and asynchronous FSMs; power, test, and ...
Santa Clara, CA · On-site
$156K - $160K/yr
SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Arithmetic circuit design, timing analysis; synchronous and asynchronous FSMs; power, test, and ...
Description As an SOC/ASIC FE Implementation Engineer, you will have responsibilities spanning ... Work on Low power design, writing UPFs, close on power intent verification at the chip level ...
Description As an SOC/ASIC FE Implementation Engineer, you will have responsibilities spanning ... Work on Low power design, writing UPFs, close on power intent verification at the chip level ...
Description As an SOC/ASIC FE Implementation Engineer, you will have responsibilities spanning ... Work on Low power design, writing UPFs, close on power intent verification at the chip level ...
Description As an SOC/ASIC FE Implementation Engineer, you will have responsibilities spanning ... Work on Low power design, writing UPFs, close on power intent verification at the chip level ...
Santa Clara, CA · On-site
$156K - $160K/yr
SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Arithmetic circuit design, timing analysis; synchronous and asynchronous FSMs; power, test, and ...
Santa Clara, CA · On-site
$156K - $160K/yr
SoC Design Engineer Job Duties: Be responsible for digital design of ASIC cores within image sensor ... Arithmetic circuit design, timing analysis; synchronous and asynchronous FSMs; power, test, and ...
Santa Clara, CA · On-site
$196K/yr
... Engineering or Electrical Engineering (or equivalent experience) Strong understanding of SoC architecture for low power mobile devices, including DVFS, power domains, and retention strategies ...
Santa Clara, CA · On-site
$196K/yr
... Engineering or Electrical Engineering (or equivalent experience) Strong understanding of SoC architecture for low power mobile devices, including DVFS, power domains, and retention strategies ...
Join the Low Power group at Silicon Technologies and contribute to the development of cutting-edge technology and capabilities for low-power chip design. Your work will fuel Apple's next-generation ...
Join the Low Power group at Silicon Technologies and contribute to the development of cutting-edge technology and capabilities for low-power chip design. Your work will fuel Apple's next-generation ...
Santa Clara, CA · On-site
$150 - $200/hr
At NVIDIA, you'll collaborate with brilliant minds to build cutting‑edge GPUs and SOCs that power everything from AI to gaming! As a Senior SOC Design Engineer, you'll work at the forefront of ...
Santa Clara, CA · On-site
$150 - $200/hr
At NVIDIA, you'll collaborate with brilliant minds to build cutting‑edge GPUs and SOCs that power everything from AI to gaming! As a Senior SOC Design Engineer, you'll work at the forefront of ...
$53.61 - $57.26
3% of jobs
$57.26 - $60.90
3% of jobs
$60.90 - $64.55
9% of jobs
$66.54 is the 25th percentile. Wages below this are outliers.
$64.55 - $68.20
18% of jobs
The median wage is $69.87 / hr.
$68.20 - $71.85
37% of jobs
$73.43 is the 75th percentile. Wages above this are outliers.
$71.85 - $75.50
12% of jobs
$75.50 - $79.15
3% of jobs
$79.15 - $82.80
0% of jobs
$82.80 - $86.45
0% of jobs
$86.45 - $90.10
8% of jobs
$90.10 - $93.75
8% of jobs
$53
$72
$93
For Low Power Soc Design Engineer jobs, the most frequently searched job titles are:

Saratoga, CA • On-site
Full-time
Medical, PTO
Re-posted 11 days ago
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