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Low Power Soc Design Engineer Jobs (NOW HIRING)

Qualcomm

Design Engineer (Low Power)

Santa Clara, CA · On-site

$176K - $264K/yr

Job Area: Engineering Group, Engineering Group > ASICS Engineering General Summary: Qualcomm ... Experience in SoC low power micro-architecture, low power design and methodology, Power Intent ...

Ambiq Micro, Inc.

Sr. Staff SoC RTL Engineer

Austin, TX · On-site

Contribute to low-power design through clock gating, power management, and efficient data movement ... Engineering, or a related field * 8+ years of hands-on ASIC or SoC RTL design experience * Strong ...

Ambiq Micro, Inc.

Sr. Staff SoC RTL Engineer

Austin, TX · On-site

Contribute to low-power design through clock gating, power management, and efficient data movement ... Engineering, or a related field * 8+ years of hands-on ASIC or SoC RTL design experience * Strong ...

Micron

HBM SOC Design Engineer

Richardson, TX · On-site

As an HBM SOC Design Engineer, you will be responsible for the design & development of next ... or low power SOC development * Familiarity with scripting languages such as Python * Experience ...

E-Space

SoC Platform Engineer

Saratoga, CA

Experience with low-power SoC design and power intent methodologies (UPF/CPF). Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.

e::space

SoC Platform Engineer

Saratoga, CA · On-site

... low-power SoC design and power intent methodologies (UPF/CPF). · Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Collaboration and ...

E-Space

SoC Platform Engineer

Saratoga, CA · On-site

... low-power SoC design and power intent methodologies (UPF/CPF). · Education: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. Collaboration and ...

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How much do low power soc design engineer jobs pay per hour?

As of Sep 9, 2026, the average hourly pay for low power soc design engineer in the United States is $72.60, according to ZipRecruiter salary data. Most workers in this role earn between $67.31 and $74.52 per hour, depending on experience, location, and employer.

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Infographic showing various Low Power Soc Design Engineer job openings in the United States as of August 2026, with employment types broken down into 88% Full Time, 7% Part Time, and 5% Contract. Highlights an 84% Physical, 5% Hybrid, and 11% Remote job distribution, with an average salary of $150,999 per year, or $72.6 per hour.

Low Power SoC Hardware Architect

Sunnyvale, CA • On-site

Baidu USA
See more jobs at Baidu USAexternal

Full-time

Re-posted 29 days ago

Job description

Do you want to be part of the AI revolution? Do you want to think out of the box, thriving on challenges in AI industry and have the desire to solve them? Do you want to work with a world-class team to explore the fast-growing AI hardware opportunities and impact on AI industry?
We're looking forward to you joining us to collaborate, contribute, and revolutionize AI silicon and system.
Description
As a Low Power SoC Architect, you will have the opportunity to independently design and define the lower power subsystem and improve the power efficiency of AI engine, in both data center and edge SoC. You will collaborate with experienced designers, RTL engineers, system and software team, to explore feasibility of ideas, proof of concept and power performance improvement.
Qualifications
  • Experience and knowledge of lower power soc architecture and deep expertise in lower power subsystem, power efficient design.
  • Lead and drive lower power & most efficient BW to power SoC design, including arch features, RTL changes for low power design, topologies with floorplan/layout and other design aspects
  • Work with IPs architects to drive low power design, methodologies, techniques, and features.
  • Drive SoC level power convergence by using existing modeling tools and techniques, and developing new state of the art tools, flows, and methodologies.
  • Experience and proof of track in power optimization: perf@watt and perf/sq.mm modeling or analysis, is a plus
  • Good teamwork with communications and support to solve all levels of architecture definition from micro-architecture to system level to software architecture.
  • Proficiency in C/C++ and scripting languages such as Perl or Python.
  • Self-driven and leadership skills.
  • Knowledge or experience in automotive industry is a plus.
  • MS or PhD in Electrical or Computer Engineering.
  • Excellent communication skills in both English and Chinese.

Culture Fit:
  • Mission alignment: If you want to be part of a team to accomplish this great mission, we will provide you the best possible platform to do that.
  • Self-directed: We work best with people that are driven, motivated, and aspire to greatness.
  • Hungry to learn: We are eager to see you learn new skills and grow.
  • Team orientation: We work in small, fast-moving teams. We watch out for each other and go after big goals together as a team.

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