... SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... RTL/design tradeoffs * Resolve design/timing/congestion and flow issues, identify potential ...
... SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... RTL/design tradeoffs * Resolve design/timing/congestion and flow issues, identify potential ...
Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You ... Learn and run RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset ...
Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You ... Learn and run RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset ...
Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You ... Learn and run RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset ...
Join the NVIDIA System-On-Chip (SOC) group as an ASIC Design Engineer and make a broad impact. You ... Learn and run RTL checks to ensure design quality (e.g., cross clock domains (CDC), clocks, reset ...
You are an experienced RTL design engineer with a passion for complex processor systems and interconnect architecture. You bring deep technical expertise, a structured problem-solving approach, and ...
You are an experienced RTL design engineer with a passion for complex processor systems and interconnect architecture. You bring deep technical expertise, a structured problem-solving approach, and ...
TITLE :- System IP/RTL Design Engineer LOCATION Austin, TX (Onsite) DURATION 6+ Months (May get extend) MODE OF INTERVIEW Onsite RATE $90 per hour on W2 Key responsibilities include: * Work on RTL ...
TITLE :- System IP/RTL Design Engineer LOCATION Austin, TX (Onsite) DURATION 6+ Months (May get extend) MODE OF INTERVIEW Onsite RATE $90 per hour on W2 Key responsibilities include: * Work on RTL ...
Senior Staff Verification Engineer
Austin, TX · On-site
$134K - $164K/yr
Prodapt's ASIC Services is a leading provider of SoC/ASIC RTL Design, UVM based verification ... As a Senior Staff System IP Design Verification engineer you will contribute to the functional ...
Senior Staff Verification Engineer
Austin, TX · On-site
$134K - $164K/yr
Prodapt's ASIC Services is a leading provider of SoC/ASIC RTL Design, UVM based verification ... As a Senior Staff System IP Design Verification engineer you will contribute to the functional ...
Design Engineering Architect
Austin, TX · On-site
Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment. Design & Microarchitecture: Define and develop microarchitectural features for IPs and ...
Design Engineering Architect
Austin, TX · On-site
Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment. Design & Microarchitecture: Define and develop microarchitectural features for IPs and ...
Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment. Design & Microarchitecture: Define and develop microarchitectural features for IPs and ...
Guide and mentor a team of RTL design engineers, fostering a collaborative and innovative environment. Design & Microarchitecture: Define and develop microarchitectural features for IPs and ...
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation for ...
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation for ...
GPU Design Engineer
Austin, TX · On-site
Provide hands-on technical leadership across RTL design and design verification, including ... Extensive experience delivering complex GPU, CPU, and/or ASIC designs from micro-architecture ...
GPU Design Engineer
Austin, TX · On-site
Provide hands-on technical leadership across RTL design and design verification, including ... Extensive experience delivering complex GPU, CPU, and/or ASIC designs from micro-architecture ...
Design Engineer III
Austin, TX · On-site
Job Title: Core Engineering - Design Engineer III Duration: 12 months with possible extension ... Minimum Qualifications Demonstrated experience with RTL-to-GDSII design flow usage and development ...
Design Engineer III
Austin, TX · On-site
Job Title: Core Engineering - Design Engineer III Duration: 12 months with possible extension ... Minimum Qualifications Demonstrated experience with RTL-to-GDSII design flow usage and development ...
As an ASIC Engineer specializing in architecture, performance and modeling, you will define and ... Collaborate with architecture, RTL design, and physical design teams to translate performance ...
As an ASIC Engineer specializing in architecture, performance and modeling, you will define and ... Collaborate with architecture, RTL design, and physical design teams to translate performance ...
As an ASIC Engineer specializing in architecture, performance and modeling, you will define and ... Collaborate with architecture, RTL design, and physical design teams to translate performance ...
As an ASIC Engineer specializing in architecture, performance and modeling, you will define and ... Collaborate with architecture, RTL design, and physical design teams to translate performance ...
As an ASIC Engineer specializing in performance and modeling, you will define and drive the ... Collaborate with architecture, RTL design, and physical design teams to translate performance ...
As an ASIC Engineer specializing in performance and modeling, you will define and drive the ... Collaborate with architecture, RTL design, and physical design teams to translate performance ...
SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... RTL design, chip bring-up, and post-silicon validation experience * Ability to work in a dynamic ...
SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... RTL design, chip bring-up, and post-silicon validation experience * Ability to work in a dynamic ...
Senior CPU RTL Design Engineer
Austin, TX · On-site
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: • Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation ...
Senior CPU RTL Design Engineer
Austin, TX · On-site
As a CPU RTL Logic Design Engineer your responsibilities will include but are not limited to: • Collaborates, drives and develops logic design, register transfer level (RTL) coding, and simulation ...
Job Title: Core Engineering - Design Engineer III Duration: 12 months with possible extension ... Minimum Qualifications Demonstrated experience with RTL-to-GDSII design flow usage and development ...
Job Title: Core Engineering - Design Engineer III Duration: 12 months with possible extension ... Minimum Qualifications Demonstrated experience with RTL-to-GDSII design flow usage and development ...
ASIC Design Engineer
Austin, TX · On-site
$130 - $210/hr
We're looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer. Ideal ...
ASIC Design Engineer
Austin, TX · On-site
$130 - $210/hr
We're looking for ASIC design engineers to contribute to and own blocks in the development of the A-0 and A-1 wafer products, across both the XPU, memory chiplet and other dies on the wafer. Ideal ...
Senior CPU RTL Design Engineer - Power Management
Austin, TX · On-site
$164K - $269K/yr
As a Senior CPU RTL Design Engineer - Power Management , you will play a critical role in designing and delivering CPU microarchitectures with strong emphasis on power management and energy-efficient ...
Senior CPU RTL Design Engineer - Power Management
Austin, TX · On-site
$164K - $269K/yr
As a Senior CPU RTL Design Engineer - Power Management , you will play a critical role in designing and delivering CPU microarchitectures with strong emphasis on power management and energy-efficient ...
Design Engineer III
Austin, TX · On-site
$120K/yr
Design Engineer III ONSITE- US: TX- Austin OR Sunnyvale office (2nd option) Salary 140 to 145K ... Minimum Qualifications Demonstrated experience with RTL-to-GDSII design flow usage and development ...
Quick apply
Design Engineer III
Austin, TX · On-site
$120K/yr
Design Engineer III ONSITE- US: TX- Austin OR Sunnyvale office (2nd option) Salary 140 to 145K ... Minimum Qualifications Demonstrated experience with RTL-to-GDSII design flow usage and development ...
Locum Asic Rtl Design Engineer information
See Leander, TX salary details
$89.8K - $99.2K
16% of jobs
$99.2K - $108.6K
3% of jobs
$108.6K - $118K
4% of jobs
$120.7K is the 25th percentile. Wages below this are outliers.
$118K - $127.3K
6% of jobs
The median wage is $133.2K / yr.
$127.3K - $136.7K
33% of jobs
$136.7K - $146.1K
3% of jobs
$146.1K - $155.5K
2% of jobs
$161.7K is the 75th percentile. Wages above this are outliers.
$155.5K - $164.9K
12% of jobs
$164.9K - $174.3K
5% of jobs
$174.3K - $183.6K
4% of jobs
$183.6K - $193K
12% of jobs
$89.8K
$143.5K
$193K
How much do locum asic rtl design engineer jobs pay per year?
As of Aug 14, 2026, the average yearly pay for locum asic rtl design engineer in Leander, TX is $143,513.00, according to ZipRecruiter salary data. Most workers in this role earn between $125,600.00 and $172,000.00 per year, depending on experience, location, and employer.
What is the difference between Locum Asic Rtl Design Engineer vs Contract Asic Rtl Design Engineer?
| Aspect | Locum Asic Rtl Design Engineer | Contract Asic Rtl Design Engineer |
|---|---|---|
| Credentials | Typically requires relevant engineering degrees and RTL design experience | Similar credentials, often with specific RTL design certifications |
| Work Environment | Temporary, short-term assignments often in multiple locations | Project-based roles, usually in a fixed location or remote |
| Employer Usage | Used by agencies or companies needing immediate, short-term expertise | Engaged by companies or staffing agencies for project-specific work |
Both roles involve RTL design skills for ASIC development, but a Locum Asic Rtl Design Engineer typically fills short-term, temporary positions, often through staffing agencies, while a Contract Asic Rtl Design Engineer is engaged for specific projects with defined durations. The main difference lies in the nature and duration of employment, but both require similar technical credentials and work environments.
What are the most commonly searched types of Asic Rtl Design Engineer jobs in Leander, TX?
The most popular types of Asic Rtl Design Engineer jobs in Leander, TX are:
What are popular job titles related to Locum Asic Rtl Design Engineer jobs in Leander, TX?
For Locum Asic Rtl Design Engineer jobs in Leander, TX, the most frequently searched job titles are:
What job categories do people searching Locum Asic Rtl Design Engineer jobs in Leander, TX look for?
The top searched job categories for Locum Asic Rtl Design Engineer jobs in Leander, TX are:
What cities near Leander, TX are hiring for Locum Asic Rtl Design Engineer jobs?
Cities near Leander, TX with the most Locum Asic Rtl Design Engineer job openings:
Full-time
Re-posted 19 days ago
SpaceX rating
8.8
Based on 147 frontline employees who took The Breakroom Quiz
15th of 72 rated aerospace companies
Job description
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)
At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
RESPONSIBILITIES:
BASIC QUALIFICATIONS:
PREFERRED SKILLS AND EXPERIENCE:
ADDITIONAL REQUIREMENTS:
ITAR REQUIREMENTS:
SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to EEOCompliance@spacex.com.
SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)
At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
RESPONSIBILITIES:
- Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
- Develop/improve physical design methodologies and automation scripts for various implementation steps
- Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
- Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
- Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop
BASIC QUALIFICATIONS:
- Bachelor's degree in electrical engineering, computer engineering or computer science
- 5+ years of ASIC and/or physical design flow development experience in industry
PREFERRED SKILLS AND EXPERIENCE:
- Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
- Strong experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
- Knowledge of deep sub-micron FinFET and CMOS solid state physics
- Knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
- Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
- Familiar with CMOS analog circuit and physical design
- Knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
- Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
- Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment
ADDITIONAL REQUIREMENTS:
- Ability to work extended hours and weekends as needed to meet critical project milestones
ITAR REQUIREMENTS:
- To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.
SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to EEOCompliance@spacex.com.
About SpaceX
Sourced by ZipRecruiter
Industry
Aerospace product and parts manufacturing, data services, guided missile and space vehicle manufacturing and satellite telecommunications
Company size
1,001 - 5,000 Employees
Headquarters location
Hawthorne, CA, US