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Lead Asic Design Verification Engineer Jobs (NOW HIRING)

Broadcom Inc.

Lead ASIC Design Engineer

San Jose, CA · On-site

$143K - $230K/yr

Lead ASIC Design EngineerSkip to main content#Lead ASIC Design Engineer page is loaded## Lead ASIC ... You will guide a cross-disciplinary team spanning analog design, physical design, and verification ...

Meta

ASIC Engineer, Design Verification

Austin, TX · On-site +1

$146K/yr

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for ...

Meta

ASIC Engineer, Design Verification

Menlo Park, CA · On-site +1

$146K/yr

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for ...

Positron AI

ASIC Design Verification Engineer

$200K - $350K/yr

Role Overview As an ASIC Design Verification Engineer, you will play a critical role in ensuring ... Lead the development of verification environments using SystemVerilog UVM * Create and maintain ...

Positron AI

ASIC Design Verification Engineer

Austin, TX · On-site

$200K - $350K/yr

Role Overview As an ASIC Design Verification Engineer, you will play a critical role in ensuring ... Lead the development of verification environments using SystemVerilog UVM * Create and maintain ...

Meta

ASIC Engineer, Design Verification

Sunnyvale, CA · On-site

$114K/yr

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for ...

Meta

ASIC Engineer, Design Verification

Austin, TX

$114K/yr

Meta is hiring ASIC Design Verification Engineer within the Infrastructure organization. We are looking for individuals with experience in Design Verification to build IP and System On Chip (SoC) for ...

K2 Space

Principal ASIC Design Verification Engineer

OR · On-site +1

$190K - $285K/yr

Take lead on large and/or complex systems. Qualifications * B.S. or M.S. in Electrical Engineering ... in ASIC/SoC verification. * Solid understanding of SystemVerilog, digital logic, RTL design, DFT ...

Cisco

ASIC Design Verification Engineer

San Jose, CA · On-site

$167K - $245K/yr

Lead architecture and implementation of scalable, reusable verification infrastructure and ... Influence ASIC architecture and design to enable robust verification and high-quality silicon.

Qualcomm

ASIC Design Verification Engineer

Santa Clara, CA · On-site

$107K - $161K/yr

As a Qualcomm ASIC Engineer, you will define, model, design (digital and/or analog), optimize, verify, validate, implement, and document IP (block/SoC) development for a variety of high performance ...

Cisco

ASIC Design Verification Engineer

San Jose, CA · On-site

$167K - $245K/yr

Lead architecture and implementation of scalable, reusable verification infrastructure and ... Influence ASIC architecture and design to enable robust verification and high-quality silicon.

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$105.5K

$149.2K

$167K

How much do lead asic design verification engineer jobs pay per year?

As of Sep 13, 2026, the average yearly pay for lead asic design verification engineer in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.

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For Lead Asic Design Verification Engineer jobs, the most frequently searched job titles are:

ASIC Design Verification Engineer

Austin, TX • On-site

Advanced Micro Devices, Inc
Computer and Electronic Product Manufacturing • 5 - 10K employees
Learn more about Advanced Micro Devices, Incexternal

$175K/yr

Full-time

Re-posted 8 days ago

Advanced Micro Devices rating

8.6

Company rating: 8.6 out of 10

Based on 13 frontline employees who took The Breakroom Quiz

Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences-from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you'll discover the real differentiator is our culture. We push the limits of innovation to solve the world's most important challenges-striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE
The AMD UMC Team (part of the MSIP organization) is looking for an ASIC Design Verification Engineer to join our growing team. We develop leading-edge DDR/LPDDR technologies powering data center and machine learning workloads. This team is part of the development for tomorrow's clients, server, embedded, graphics, and semi-custom chips. You will be involved in all aspects of IP verification starting from helping to create a verification architecture, defining test plans, verification environment development, and verification closure/sign-off.
As a key contributor to the success of AMD's IP, you will be part of a leading team to drive and improve AMD's abilities to deliver the highest quality, industry leading technologies to market. The NBIO Team fosters and encourages continuous technical innovation to showcase successes as well as facilitate continuous career development.
THE PERSON
I am a strong analytical thinker with excellent problem-solving abilities and keen attention to detail. I work well in team environments and communicate effectively, drawing on solid interpersonal skills. A self-starter by nature, I independently drive tasks to completion and thrive in fast-paced, multi-project settings that use state-of-the-art tools and technologies. I maintain a continuous improvement mindset and bring strong expertise as a verification lead and architect.
KEY RESPONSIBILITIES
  • Collaborate with IP architects to come up with verification architecture and development plans
  • Participate in verification of complex IP blocks and take end-to-end ownership of key features for all projects
  • Work on test plans, verification environment development, regression, and coverage closure
  • Develop modifying and maintaining VIP, libraries, verification environments, testcases (random and directed) using System Verilog/UVM/SystemC
  • Triaging and Debugging Regressions
  • Analyzing code and functional coverage
  • Deploying industry-leading verification methodologies such as UVM and formal Verification
  • Reproducing functional bugs found in post-silicon in dynamic simulation and/or formal verification environments
  • Conducting and participating in code reviews
  • Develop and maintain scripts and tools to continuously improve in engineering infrastructure, methodology and execution

PREFERRED EXPERIENCE
  • ASIC verification experience
  • Strong understanding of digital design and computer architecture
  • Proficient in Verilog, System Verilog, C/C++, UVM, OOP, and working in Linux and Windows environments
  • ASIC design knowledge and be able to debug System Verilog RTL code using simulation tools
  • Experience in security verification would be an asset

ACADEMIC CREDENTIALS
  • BS/MS degree in Engineering (Electrical, Electronics, Computer) or Computer Science.

This role is not eligible for Visa sponsorship.
#LI-DP1
#LI-HYBRID
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD's "Responsible AI Policy" is available here.
This posting is for an existing vacancy.

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