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Layout Design Engineer Jobs in California (NOW HIRING)

TetraMem Inc

Analog Layout Engineer

San Jose, CA · On-site

$110K - $300K/yr

This role requires a strong understanding of analog design principles and the ability to work closely with the design team to meet project goals. Responsibilities: * Lead a team of layout engineers ...

OMNIVISION

Analog Design Engineer

Santa Clara, CA · On-site

$110K - $140K/yr

Description We are looking for qualified Analog design engineers who have a good understanding of ... Perform the block level and transistor level layout design and optimization of sensor array readout ...

Apex Informatics

Design Engineer III

Sunnyvale, CA · On-site

Design Engineer III Job Id: 56823-1 Location: Sunnyvale, CA Qualifications • BS in EE or ... Knowledge of multilayer PCB layout, fabrication and assembly techniques including blind/buried vias ...

OMNIVISION

Analog Design Engineer

Irvine, CA · On-site

$110K - $150K/yr

Description We are looking for Image Sensor Analog Design Engineer for design and development of ... Perform the block level and transistor level layout design and optimization of sensor array readout ...

OmniVision Technologies

Analog Design Engineer

Irvine, CA

$110K - $150K/yr

We are looking forImage Sensor Analog Design Engineer for design and development of next generation ... Perform the block level and transistor level layout design and optimization of sensor array readout ...

OMNIVISION

Analog Design Engineer

Irvine, CA

$110K - $150K/yr

We are looking for Image Sensor Analog Design Engineer for design and development of next ... Perform the block level and transistor level layout design and optimization of sensor array readout ...

OMNIVISION

Analog Design Engineer

Santa Clara, CA

$110K - $140K/yr

We are looking for qualified Analog design engineers who have a good understanding of analog ... Perform the block level and transistor level layout design and optimization of sensor array readout ...

OMNIVISION

Analog Design Engineer

Irvine, CA

We are looking for Image Sensor Analog Design Engineer for design and development of next ... Perform the block level and transistor level layout design and optimization of sensor array readout ...

OMNIVISION

Analog Design Engineer

Santa Clara, CA

We are looking for qualified Analog design engineers who have a good understanding of analog ... Perform the block level and transistor level layout design and optimization of sensor array readout ...

OMNIVISION

Sr. Analog Design Engineer

Santa Clara, CA · On-site

$130K - $150K/yr

Perform the block level and transistor level layout design and optimization of sensor array readout ... Collaborate with verification, process, test, and application engineers to debug, characterize and ...

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All JobsLayout Design Engineer JobsLayout Design Engineer Jobs in California

Layout Design Engineer information

See California salary details

$44.4K

$119.3K

$183.1K

How much do layout design engineer jobs pay per year?

As of Jun 30, 2026, the average yearly pay for layout design engineer in California is $119,266.00, according to ZipRecruiter salary data. Most workers in this role earn between $88,800.00 and $142,100.00 per year, depending on experience, location, and employer.

What engineers make $500,000?

Senior engineers in specialized fields such as petroleum, aerospace, or software engineering can earn $500,000 or more annually, often through a combination of base salary, bonuses, and stock options. High-level roles typically require extensive experience, advanced skills, and sometimes professional certifications or advanced degrees.

What does a layout design engineer do?

A layout design engineer develops and optimizes the physical arrangement of electronic components on integrated circuits or printed circuit boards using specialized CAD tools. They ensure the design meets electrical, thermal, and manufacturing requirements, often working closely with circuit designers and manufacturing teams. Proficiency in electronic design automation (EDA) software and understanding of semiconductor fabrication processes are essential for this role.

How much do layout engineers make?

Layout design engineers typically earn a median annual salary ranging from $70,000 to $120,000, depending on experience, location, and industry. They often work with electronic design automation tools and require knowledge of semiconductor fabrication processes. Salaries can vary based on certifications and the complexity of projects handled.

What is a Layout Design Engineer job?

A Layout Design Engineer is responsible for designing and optimizing the physical layout of integrated circuits (ICs) in semiconductor chips. They work closely with circuit designers to ensure that the layout meets performance, power, and area constraints while adhering to manufacturing and design rules. Their role involves using EDA tools for placement, routing, and verification of chip layouts. They also conduct design rule checks (DRC) and layout versus schematic (LVS) verification to ensure design accuracy.

What are the key skills and qualifications needed to thrive in the Layout Design Engineer position, and why are they important?

To thrive as a Layout Design Engineer, you need strong skills in electronic circuit design, physical layout principles, and a background in electrical or electronics engineering, typically supported by a relevant bachelor's degree. Proficiency with EDA tools such as Cadence, Mentor Graphics, or Synopsys, and knowledge of industry standards (e.g., IPC) are essential. Exceptional attention to detail, problem-solving, and effective teamwork and communication skills help set candidates apart. These capabilities ensure precise, manufacturable layouts and smooth collaboration with multidisciplinary teams to meet project goals and deadlines.

What does a typical day look like for a Layout Design Engineer?

A typical day for a Layout Design Engineer involves translating schematic designs into detailed physical layouts using specialized CAD tools, collaborating closely with circuit designers to optimize for performance and manufacturability. You may spend time reviewing design rule checks (DRC), participating in team meetings to discuss project progress or resolve technical challenges, and coordinating with fabrication or test engineers to ensure successful implementation. The role requires both independent focus and frequent teamwork, offering a dynamic mix of technical and collaborative tasks. Depending on the company, you might also be involved in process improvement initiatives or mentoring junior engineers as you gain experience.

What's a design engineer's salary?

A layout design engineer's salary typically ranges from $70,000 to $110,000 annually, depending on experience, location, and industry. Senior roles or those with specialized skills in CAD tools and circuit design may earn higher compensation.
What are popular job titles related to Layout Design Engineer jobs in California? For Layout Design Engineer jobs in California, the most frequently searched job titles are:
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What cities in California are hiring for Layout Design Engineer jobs? Cities in California with the most Layout Design Engineer job openings:
Layout Design Engineer jobs near you
Sr. Analog Physical Design Engineer

Sr. Analog Physical Design Engineer

OmniVision Technologies

Santa Clara, CA • On-site

$156K - $160K/yr

Other

Posted 5 days ago

Job description

Job Title: Sr. Analog Physical Design Engineer
Job Duties:
  • Work on detailed column ADC circuit design, with a focus on column layout design. Collaborating with other column ADC designers to optimize column ADC's performance with minimum silicon area.
  • Conduct cross products column ADC layout comparison and IP layout development and maintenance.
  • Perform RCX extraction of column circuit and critical signals parasitic analysis and propose optimized design to improve column ADC performance and image quality.
  • Conduct image sensor pixel array and column ADC supply analysis using Totem or other methodologies, including worst case P2P resistor extraction, and optimize chip floorplan and power routing.
  • Study design rules for new processes and provide physical design guidelines to the design team. Debug and develop Calibre svrf files when needed.
  • Apply SKILL script to improve productivity and design robustness.
  • Responsible for full-custom analog IC layout and physical verification (DRC/ANT/DFM/ERC/LVS) using industry-standard tools like Cadence Virtuoso and Calibre.
  • Execute top-level layout and coordinate layout resources and schedules for all modules.
  • Perform floor planning and placements including pad locations, power/clock domain planning, ESD, integration of AMS and digital blocks, and chip-level routing strategy.
  • Lead top-level implementation from floorplan through GDS tape-out.
  • Develop and maintain layout methodologies and documentation to ensure efficient and consistent design practices.
Requirements:
Require Master's degree or foreign equivalent degree in Electrical Engineering, Electronics Engineering, or a closely related field.
Require 2 years of experience in CMOS image sensor IC layout design.
Require the following experience or skills:
  • Semiconductor process and device fundamentals, with expertise in addressing advanced technology nodes challenges.
  • Experience in image sensor manufacturing technology, performance metrics, and system-level integration in camera applications.
  • Experience with industry standard EDA tools, such as Cadence Virtuoso, PVS, Spectre, Innovus, Skipper, Siemens Calibre, Synopsys Hspice, Design Compiler, IC Compiler, PrimeTime, Laker and P2P.
  • Front-end and back-end ASIC design flows.
  • Experience in stacked chip process flow and related design considerations.
  • Skills in interpreting physical verification reports (DRC, DFM, ERC, LVS, etc.) and understanding SVRF rule files.
  • Advanced layout skills such ascommon-centroid layouts, symmetrical layouts, use of dummy devices, matching, ESD, latch-up, antenna effects, etc.
  • Understanding of layout impact on device matching, noise coupling, guard-ring, electromigration, isolation and IR drop.
  • Developing CAD flow automation using scripting languages like Perl, Skill, and Tcl.
  • Expertise in low-power, high-precision, high speed analog layout design techniques.
  • Solving crosstalk challenges between adjacent column ADCs in image sensor circuits.
Annual base salary for this role in California, US is expected to be between $156,853 - $160,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.

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