Work closely with other engineering teams, such as analog and digital, to ensure seamless ... SRAM, DRAM, Flash or emerging NVM technologies * Strong understanding of layout design including ...
Work closely with other engineering teams, such as analog and digital, to ensure seamless ... SRAM, DRAM, Flash or emerging NVM technologies * Strong understanding of layout design including ...
Senior Design Engineer
Annapolis, MD · On-site
$135K - $230K/yr
As the Senior Design Engineer, you will develop, maintain and test high-performance FPGA computing ... Develop FPGA interfaces to SRAM/DRAM, Multi-Gigabit Transceivers, ADCs/DACs * Create example ...
Senior Design Engineer
Annapolis, MD · On-site
$135K - $230K/yr
As the Senior Design Engineer, you will develop, maintain and test high-performance FPGA computing ... Develop FPGA interfaces to SRAM/DRAM, Multi-Gigabit Transceivers, ADCs/DACs * Create example ...
Design Engineer
Kansas City, MO · On-site
Design Engineer Department: Engineering Reports to: Engineering Manager Supervisory ... Previous work or internship experience in the Food Industry is preferred but not required. Other ...
Design Engineer
Kansas City, MO · On-site
Design Engineer Department: Engineering Reports to: Engineering Manager Supervisory ... Previous work or internship experience in the Food Industry is preferred but not required. Other ...
Design Engineer
$68K - $80K/yr
Design and modify components and assemblies using SolidWorks * Create detailed 2D drawings with ... Bachelor's degree in Mechanical Engineering * 0-3 years of engineering experience (internships/co ...
Quick apply
Design Engineer
$68K - $80K/yr
Design and modify components and assemblies using SolidWorks * Create detailed 2D drawings with ... Bachelor's degree in Mechanical Engineering * 0-3 years of engineering experience (internships/co ...
CPU Cache Microarchitect/RTL Engineer
$181.10K - $318.40K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$181.10K - $318.40K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$181.10K - $318.40K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$181.10K - $318.40K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$147.40K - $272.10K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$147.40K - $272.10K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
Exposure to memory design (DRAM, NAND, SRAM) or high-speed circuit design * Experience with layout tools and physical design methodologies * Knowledge of scripting or programming (e.g., Python, TCL ...
Exposure to memory design (DRAM, NAND, SRAM) or high-speed circuit design * Experience with layout tools and physical design methodologies * Knowledge of scripting or programming (e.g., Python, TCL ...
Design Engineer I CA | GA | NY | CR About Sherwood Design Engineers Sherwood is a civil and ... Typically industry internship experience * Bachelor's degree in Engineering - Civil and/or ...
Design Engineer I CA | GA | NY | CR About Sherwood Design Engineers Sherwood is a civil and ... Typically industry internship experience * Bachelor's degree in Engineering - Civil and/or ...
DRAM Design Engineer
Boise, ID · On-site
Exposure to memory design (DRAM, NAND, SRAM) or high-speed circuit design * Experience with layout tools and physical design methodologies * Knowledge of scripting or programming (e.g., Python, TCL ...
DRAM Design Engineer
Boise, ID · On-site
Exposure to memory design (DRAM, NAND, SRAM) or high-speed circuit design * Experience with layout tools and physical design methodologies * Knowledge of scripting or programming (e.g., Python, TCL ...
CPU Cache Microarchitect/RTL Engineer
Beaverton, OR · On-site
$181.10K - $318.40K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
Beaverton, OR · On-site
$181.10K - $318.40K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
Design Engineer
Winn, MI · On-site
The Design Engineer will be assigned design projects for product modifications and new products ... internship and co-op experiences.
Design Engineer
Winn, MI · On-site
The Design Engineer will be assigned design projects for product modifications and new products ... internship and co-op experiences.
CPU Cache Microarchitect/RTL Engineer
$181.10K - $318.40K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$181.10K - $318.40K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
Design Engineer
Winn, MI · On-site
The Design Engineer will be assigned design projects for product modifications and new products ... internship and co-op experiences.
Design Engineer
Winn, MI · On-site
The Design Engineer will be assigned design projects for product modifications and new products ... internship and co-op experiences.
Staff Physical Design Engineer
Richardson, TX · On-site
$123.50K - $127.10K/yr
Collaborate with the Architect, Front End Design, and CAD teams to deliver best-in-class designs. Assist Front End Design and Integration Engineers with SRAM/RF specification and synthesis design ...
Staff Physical Design Engineer
Richardson, TX · On-site
$123.50K - $127.10K/yr
Collaborate with the Architect, Front End Design, and CAD teams to deliver best-in-class designs. Assist Front End Design and Integration Engineers with SRAM/RF specification and synthesis design ...
Staff Physical Design Engineer
$123.50K - $127.10K/yr
Collaborate with the Architect, Front End Design, and CAD teams to deliver best-in-class designs. Assist Front End Design and Integration Engineers with SRAM/RF specification and synthesis design ...
Staff Physical Design Engineer
$123.50K - $127.10K/yr
Collaborate with the Architect, Front End Design, and CAD teams to deliver best-in-class designs. Assist Front End Design and Integration Engineers with SRAM/RF specification and synthesis design ...
CPU Cache Microarchitect/RTL Engineer
$147.40K - $272.10K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
CPU Cache Microarchitect/RTL Engineer
$147.40K - $272.10K/yr
... SRAM design basics, multiple clock/power domains and power management strategies, prefetchers ... C++ programming Experience using an interpretive language such as Perl or Python Minimum ...
Design Engineer I (Entry-Level / Junior) Location: Fort Worth, TX (HQ) Department: Engineering ... internships count) Success Profile * Coachable and detail-oriented * Willing to be in the shop and ...
Design Engineer I (Entry-Level / Junior) Location: Fort Worth, TX (HQ) Department: Engineering ... internships count) Success Profile * Coachable and detail-oriented * Willing to be in the shop and ...
Senior Staff Analog Layout SRAM Engineer
Burlington, VT · On-site
$104.40K - $140.50K/yr
Support optimization, debug, and design-rule closure * Proficiency with Cadence Virtuoso and ... every stage - from internship to retirement and through life's most important moments. Our ...
Senior Staff Analog Layout SRAM Engineer
Burlington, VT · On-site
$104.40K - $140.50K/yr
Support optimization, debug, and design-rule closure * Proficiency with Cadence Virtuoso and ... every stage - from internship to retirement and through life's most important moments. Our ...
The Design Engineer collaborates with experienced engineers to develop and refine product and ... Bachelor's degree in engineering * 1+ years related experience, including internships Physical ...
The Design Engineer collaborates with experienced engineers to develop and refine product and ... Bachelor's degree in engineering * 1+ years related experience, including internships Physical ...
Internship Sram Design Engineer information
See salary details
$9.13 - $11.65
9% of jobs
$11.65 - $14.16
8% of jobs
$14.81 is the 25th percentile. Wages below this are outliers.
$14.16 - $16.67
28% of jobs
The median wage is $17.34 / hr.
$16.67 - $19.19
16% of jobs
$20.91 is the 75th percentile. Wages above this are outliers.
$19.19 - $21.70
20% of jobs
$21.70 - $24.21
9% of jobs
$24.21 - $26.73
4% of jobs
$26.73 - $29.24
1% of jobs
$29.24 - $31.75
1% of jobs
$31.75 - $34.27
1% of jobs
$34.27 - $36.78
2% of jobs
$9
$19
$36
How much do internship sram design engineer jobs pay per hour?
What are the key skills and qualifications needed to thrive as an Internship SRAM Design Engineer, and why are they important?
What are some common challenges faced by Internship SRAM Design Engineers, and how can they be overcome?
What are Internship SRAM Design Engineers?
What is the difference between Internship Sram Design Engineer vs Sram Design Engineer?
| Aspect | Internship Sram Design Engineer | Sram Design Engineer |
|---|---|---|
| Qualifications | Enrolled in or recent graduate of relevant engineering program | Bachelor's or Master's in Electrical/Electronic Engineering |
| Work Environment | Internship, supervised, learning-focused | Full-time, project-driven, professional setting |
| Responsibilities | Assisting in design tasks, learning industry tools | Designing, testing, and developing SRAM components |
| Duration | Typically 3-6 months | Full-time, ongoing role |
The main difference is that an Internship Sram Design Engineer is a temporary, learning-focused position for students or recent graduates, while a Sram Design Engineer is a full-time professional responsible for designing SRAM components. Interns gain hands-on experience, whereas full engineers lead projects and make design decisions.
Full-time
Medical, Retirement, PTO
Posted 20 days ago
Job description
TetraMem is a fast-growing well-funded startup company working on the next generation of computing platforms with unique ReRAM-based in-memory computing technologies. We are hiring in multiple positions from software to hardware.
We offer a very competitive compensation, commensurate with experience, and a full benefits package including medical, professional PTO, 401k, and other perks.
- Design the memory IC projects from concept to tape-out
- Define and implement memory architectures and circuits, optimizing for speed, power, and area.
- Develop comprehensive test plans, simulate designs, and debug issues.
- Work on performance improvements, analyzing and addressing bottlenecks in memory designs.
- Work closely with other engineering teams, such as analog and digital, to ensure seamless integration with overall product development.
- Investigate and resolve design issues and participate in silicon bring-up and validation activities.
MS or PhD in Electrical Engineering with emphasis on CMOS memory, digital or mixed-signal design
5+ years of experience in circuit design in advanced CMOS processes (PhD experience may be considered as experience), successful tape-out experience with leading foundries
Experience in memory circuit design in one of: SRAM, DRAM, Flash or emerging NVM technologies
Strong understanding of layout design including layout dependent effects, pitch matching, and design for manufacturing
Familiar with common EDA environment tools, CAD tools and memory design methodology including design, simulation, layout, and verification tools (e.g. Synopsys Cadence, Mentor Graphics etc.).
Ability to create innovative architecture and circuit solutions to customer requirements
Ability to work in startup environment and work both independently and as a team player
Experience in one or more of the following areas considered a strong plus:
Hands-on production experience with key memory blocks such as sense amplifier, charge pump, read/write assist circuit, PVT tracker, power gating etc
Familiar with memory controller or memory interface
Experience with emerging non-volatile memory
All your information will be kept confidential according to EEO guidelines.
About TetraMem Accelerate The World
Sourced by ZipRecruiter
Industry
Computer and peripheral equipment manufacturing
Company size
11 - 50 Employees
Headquarters location
Fremont, CA, US
Year founded
2018