Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...
Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...
Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...
Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...
Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...
Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...
Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...
Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In ...
CA · On-site
... for SRAM and memory blocks, covering array layout, periphery positioning, power grid design ... engineers, and help raise layout quality and execution rigor across the team. Have a BSEE or ...
CA · On-site
... for SRAM and memory blocks, covering array layout, periphery positioning, power grid design ... engineers, and help raise layout quality and execution rigor across the team. Have a BSEE or ...
Role and Responsibilities As a Senior Staff Memory/SRAM Circuit Design Engineer, you will help drive the development of high-performance, power- and area-efficient SRAM and custom memory macros that ...
Role and Responsibilities As a Senior Staff Memory/SRAM Circuit Design Engineer, you will help drive the development of high-performance, power- and area-efficient SRAM and custom memory macros that ...
Role and Responsibilities As a Senior Staff Memory/SRAM Circuit Design Engineer, you will help drive the development of high-performance, power- and area-efficient SRAM and custom memory macros that ...
Role and Responsibilities As a Senior Staff Memory/SRAM Circuit Design Engineer, you will help drive the development of high-performance, power- and area-efficient SRAM and custom memory macros that ...
SRAM Mask Layout Engineer at Santa clara,CA Here is the JD for your reference : Sr. SRAM Layout Design Engineer Santa Clara,CA Longterm Contract What you will be doing: • Manage the complete custom ...
SRAM Mask Layout Engineer at Santa clara,CA Here is the JD for your reference : Sr. SRAM Layout Design Engineer Santa Clara,CA Longterm Contract What you will be doing: • Manage the complete custom ...
Memory Design Engineer
Troy, MI · On-site
Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis and Monte Carlo Simulations. * Exposure to full embedded memory design flow: Architecture, circuit design, physical ...
Quick apply
Memory Design Engineer
Troy, MI · On-site
Good understanding of SRAM architecture, Critical Path Modelling, Full Cut Analysis and Monte Carlo Simulations. * Exposure to full embedded memory design flow: Architecture, circuit design, physical ...
Exposure to complete design cycle of SRAM memory and compiler development * Supervise layout engineers and review layout for optimality * Have the ability to come up with comprehensive design ...
Exposure to complete design cycle of SRAM memory and compiler development * Supervise layout engineers and review layout for optimality * Have the ability to come up with comprehensive design ...
Principal Circuit Design Engineer
Raleigh, NC · On-site
$188K - $304K/yr
Responsibilities * Collaborate with SoC designers to develop Memory SRAM and Register file ... design value propositions and risks. * Effective debug skills. #SCHIE Silicon Engineering IC5 - The ...
Principal Circuit Design Engineer
Raleigh, NC · On-site
$188K - $304K/yr
Responsibilities * Collaborate with SoC designers to develop Memory SRAM and Register file ... design value propositions and risks. * Effective debug skills. #SCHIE Silicon Engineering IC5 - The ...
Responsibilities include SRAM bitcell design, process integration, SWR/DOE (experiments) definition ... Master of Science degree in Electrical Engineering or related degree * 10 + years of relevant ...
Responsibilities include SRAM bitcell design, process integration, SWR/DOE (experiments) definition ... Master of Science degree in Electrical Engineering or related degree * 10 + years of relevant ...
Responsibilities include SRAM bitcell design, process integration, SWR/DOE (experiments) definition ... Engineer your future. We empower our employees to truly own their career and development. Come ...
Responsibilities include SRAM bitcell design, process integration, SWR/DOE (experiments) definition ... Engineer your future. We empower our employees to truly own their career and development. Come ...
We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...
We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...
Responsibilities include SRAM bitcell design, process integration, SWR/DOE (experiments) definition ... Master of Science degree in Electrical Engineering or related degree * 10 + years of relevant ...
Responsibilities include SRAM bitcell design, process integration, SWR/DOE (experiments) definition ... Master of Science degree in Electrical Engineering or related degree * 10 + years of relevant ...
... of SRAM and register files. - Collaborate with design and CAD team to optimize design flows and ... programming skills in languages like: SKILL, Perl, Python, TCL, Shell. - Ability to work ...
... of SRAM and register files. - Collaborate with design and CAD team to optimize design flows and ... programming skills in languages like: SKILL, Perl, Python, TCL, Shell. - Ability to work ...
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... with SRAM design is also a plus * Hands-on experience with NVM test chip design, bring-up, and ...
For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal ... with SRAM design is also a plus * Hands-on experience with NVM test chip design, bring-up, and ...
... internships or full-time employment Or a PhD in Electrical Engineering, Computer Engineering ... Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ...
... internships or full-time employment Or a PhD in Electrical Engineering, Computer Engineering ... Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ...
... internships or full-time employment Or a PhD in Electrical Engineering, Computer Engineering ... Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ...
... internships or full-time employment Or a PhD in Electrical Engineering, Computer Engineering ... Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ...
... internships or full-time employment Or a PhD in Electrical Engineering, Computer Engineering ... Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ...
... internships or full-time employment Or a PhD in Electrical Engineering, Computer Engineering ... Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ...
Internship Sram Design Engineer information
See salary details
$9.13 - $11.65
9% of jobs
$11.65 - $14.16
8% of jobs
$14.81 is the 25th percentile. Wages below this are outliers.
$14.16 - $16.67
28% of jobs
The median wage is $17.34 / hr.
$16.67 - $19.19
16% of jobs
$20.91 is the 75th percentile. Wages above this are outliers.
$19.19 - $21.70
20% of jobs
$21.70 - $24.21
9% of jobs
$24.21 - $26.73
4% of jobs
$26.73 - $29.24
1% of jobs
$29.24 - $31.75
1% of jobs
$31.75 - $34.27
1% of jobs
$34.27 - $36.78
2% of jobs
$9
$19
$36
How much do internship sram design engineer jobs pay per hour?
As of Jul 15, 2026, the average hourly pay for internship sram design engineer in the United States is $19.38, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $21.63 per hour, depending on experience, location, and employer.
What is the difference between Internship Sram Design Engineer vs Sram Design Engineer?
| Aspect | Internship Sram Design Engineer | Sram Design Engineer |
|---|---|---|
| Qualifications | Enrolled in or recent graduate of relevant engineering program | Bachelor's or Master's in Electrical/Electronic Engineering |
| Work Environment | Internship, supervised, learning-focused | Full-time, project-driven, professional setting |
| Responsibilities | Assisting in design tasks, learning industry tools | Designing, testing, and developing SRAM components |
| Duration | Typically 3-6 months | Full-time, ongoing role |
The main difference is that an Internship Sram Design Engineer is a temporary, learning-focused position for students or recent graduates, while a Sram Design Engineer is a full-time professional responsible for designing SRAM components. Interns gain hands-on experience, whereas full engineers lead projects and make design decisions.
What are Internship SRAM Design Engineers?
Internship SRAM Design Engineers are students or recent graduates who work temporarily with engineering teams to help design, develop, and test Static Random-Access Memory (SRAM) components. They typically assist with circuit design, simulation, layout, and verification processes under the supervision of senior engineers. This role provides hands-on experience in integrated circuit (IC) design, exposure to industry-standard tools, and an understanding of the semiconductor development cycle. Interns also gain valuable insights into teamwork, problem-solving, and the application of theoretical knowledge in real-world projects.
What are the key skills and qualifications needed to thrive as an Internship SRAM Design Engineer, and why are they important?
To thrive as an Internship SRAM Design Engineer, you need a solid understanding of digital circuit design, CMOS fundamentals, and basic computer architecture, typically supported by coursework in electrical or computer engineering. Familiarity with EDA tools such as Cadence, Synopsys, and simulation software, as well as scripting languages like Python or TCL, is highly valued. Strong analytical thinking, attention to detail, and effective teamwork skills help interns excel in collaborative and problem-solving environments. These skills are crucial for accurately designing, simulating, and verifying SRAM circuits, ultimately contributing to high-performance and reliable chip designs.
What are some common challenges faced by Internship SRAM Design Engineers, and how can they be overcome?
Internship SRAM Design Engineers often encounter challenges such as understanding complex circuit design principles, adapting to specialized CAD tools, and keeping up with fast-paced project timelines. To overcome these hurdles, it's helpful to actively seek mentorship from senior engineers, engage in hands-on practice with design software, and participate in team design reviews. Embracing feedback and asking questions can accelerate learning, while staying organized helps manage multiple tasks effectively.
What cities are hiring for Internship Sram Design Engineer jobs? Cities with the most Internship Sram Design Engineer job openings:
What are the most commonly searched types of Sram Design Engineer jobs? The most popular types of Sram Design Engineer jobs are:
What states have the most Internship Sram Design Engineer jobs? States with the most job openings for Internship Sram Design Engineer jobs include:
Full-time
Posted 2 days ago
Nvidia rating
9.3
Based on 5 frontline employees who took The Breakroom Quiz
15th of 209 rated software companies
Job description
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology-and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent. As an NVIDIAN, you'll be immersed in a diverse, supportive environment where everyone is inspired to do their best work. Come join the team and see how you can make a lasting impact on the world.
Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In this role, you will build custom memory layouts from initial floorplanning through DRC/LVS-clean tapeout, working closely with circuit design, physical design, integration, CAD, and foundry teams. This is a senior individual contributor role for someone who can produce complex layouts, make informed advanced-node tradeoffs, improve layout methodology, and guide junior engineers.
What you will be doing:
What we need to see:
Ways to stand out from the crowd:
Widely considered to be one of the technology world's most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/
#LI-Hybrid
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 132,000 USD - 207,000 USD for Level 4, and 148,000 USD - 235,750 USD for Level 5.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until June 17, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
Are you looking for a Mask layout Design Engineer role? We are seeking a hands-on Senior SRAM Layout Engineer to lead the physical layout creation for SRAM and memory IP in advanced CMOS nodes. In this role, you will build custom memory layouts from initial floorplanning through DRC/LVS-clean tapeout, working closely with circuit design, physical design, integration, CAD, and foundry teams. This is a senior individual contributor role for someone who can produce complex layouts, make informed advanced-node tradeoffs, improve layout methodology, and guide junior engineers.
What you will be doing:
- Manage the complete custom layout process for SRAM bitcell arrays, memory periphery, test structures, and memory macros in advanced CMOS technologies.
- Develop and improve floorplans for SRAM and memory blocks, covering array layout, periphery positioning, power grid design, routing channels, and macro assembly.
- Carry out, debug, and complete DRC, LVS, ERC, antenna, and associated physical verification checks with tools such as Calibre, ICV, or similar workflows.
- Support EM/IR review, power integrity, density/fill, DFM, dummy insertion, layout-dependent effects, and other requirements for tapeout.
- Collaborate with circuit designers to convert schematics into layouts, ensuring matching, symmetry, shielding, parasitic targets, and reliability constraints are maintained.
- Collaborate with PnR and integration teams to resolve top-level DRC/LVS, pin access, boundary, routing, power-grid, and macro-integration issues.
- Implement and advance layout methodology, checklists, reusable practices, and quality standards for consistent memory IP delivery.
- Collaborate with foundry, CAD, and methodology teams on rule interpretation, deck behavior, waivers, and advanced-node process constraints.
- Review layouts, mentor junior engineers, and help raise layout quality and execution rigor across the team.
What we need to see:
- Have a BSEE or equivalent experience
- 10+ years of custom IC layout experience, including 5+ years in SRAM, memory compiler, or full-custom memory IP layout.
- Hands-on participation in advanced CMOS technology initiatives, preferably concentrating on FinFET or GAA nodes at 5nm, 3nm, or smaller dimensions.
- Solid grasp of SRAM and memory layout principles.
- Extensive experience in Cadence Virtuoso applied to custom layout creation and assessment.
- Extensive experience in DRC/LVS debugging using Calibre, ICV, or similar physical verification tools.
- Experience with floorplanning, block-level routing, macro assembly, pin planning, boundary/interface management, and top-level physical verification.
- Direct familiarity with advanced-node layout limitations and layout-dependent phenomena, including LOD, density/fill, matching, symmetry, shielding, electromigration, IR drop, and DFM or similar expertise.
- Ability to work effectively with circuit build, physical build, integration, CAD, and foundry teams.
- Clear communication, strong ownership, good judgment, and the ability to mentor other engineers.
Ways to stand out from the crowd:
- Experience in scripting using Cadence SKILL, Python, or comparable languages for layout automation, checks, reporting, or improving workflows.
- Strong familiarity with EM/IR, reliability, density, fill, DFM, and post-processing closure at both IP and top level.
Widely considered to be one of the technology world's most desirable employers, NVIDIA offers highly competitive salaries and a comprehensive benefits package. As you plan your future, see what we can offer to you and your family www.nvidiabenefits.com/
#LI-Hybrid
Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is 132,000 USD - 207,000 USD for Level 4, and 148,000 USD - 235,750 USD for Level 5.
You will also be eligible for equity and benefits.
Applications for this job will be accepted at least until June 17, 2026.
This posting is for an existing vacancy.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.
About Nvidia
Sourced by ZipRecruiter
NVIDIA has been transforming computer graphics, PC gaming, and accelerated computing for more than 25 years. It's a unique legacy of innovation that's fueled by great technology--and amazing people. Today, we're tapping into the unlimited potential of AI to define the next era of computing. An era in which our GPU acts as the brains of computers, robots, and self-driving cars that can understand the world. Doing what's never been done before takes vision, innovation, and the world's best talent.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1993