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Internship Sram Design Engineer Jobs (NOW HIRING)

Intel

Memory Circuit Design Engineer

Hillsboro, OR

$122.44K - $232.19K/yr

D with 1-2 years of professional experience gained through either internships or full-time ... Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ...

Intel

Memory Circuit Design Engineer

Santa Clara, CA

$122.44K - $232.19K/yr

D with 1-2 years of professional experience gained through either internships or full-time ... Design, characterization, and verification of custom memory circuits such as SRAM, Register Files ...

Apple

Circuit Design Automation Engineer

Austin, TX

$172.10K - $305.60K/yr

... of SRAM and register files. - Collaborate with design and CAD team to optimize design flows and ... programming skills in languages like: SKILL, Perl, Python, TCL, Shell. - Ability to work ...

Apple

Circuit Design Automation Engineer

Austin, TX

$172.10K - $305.60K/yr

... of SRAM and register files. - Collaborate with design and CAD team to optimize design flows and ... programming skills in languages like: SKILL, Perl, Python, TCL, Shell. - Ability to work ...

Apple

Custom Circuits Design Engineer

Beaverton, OR

$147.40K - $272.10K/yr

We have an extraordinary opportunity for Circuits Engineers to design advanced custom digital megacells (SRAM memories, on-chip sensors, ML accelerators data path) used in a high performance / low ...

Cochran

Design Engineer

Union, MO

We are seeking a motivated and detail-oriented Design Engineer to join our civil engineering design ... Previous internship or co-op experience with a civil engineering or consulting firm * Familiarity ...

Cochran

Design Engineer

Union, MO

We are seeking a motivated and detail-oriented Design Engineer to join our civil engineering design ... Previous internship or co-op experience with a civil engineering or consulting firm * Familiarity ...

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How much do internship sram design engineer jobs pay per hour?

As of May 30, 2026, the average hourly pay for internship sram design engineer in the United States is $19.38, according to ZipRecruiter salary data. Most workers in this role earn between $14.42 and $21.63 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an Internship SRAM Design Engineer, and why are they important?

To thrive as an Internship SRAM Design Engineer, you need a solid understanding of digital circuit design, CMOS fundamentals, and basic computer architecture, typically supported by coursework in electrical or computer engineering. Familiarity with EDA tools such as Cadence, Synopsys, and simulation software, as well as scripting languages like Python or TCL, is highly valued. Strong analytical thinking, attention to detail, and effective teamwork skills help interns excel in collaborative and problem-solving environments. These skills are crucial for accurately designing, simulating, and verifying SRAM circuits, ultimately contributing to high-performance and reliable chip designs.

What are some common challenges faced by Internship SRAM Design Engineers, and how can they be overcome?

Internship SRAM Design Engineers often encounter challenges such as understanding complex circuit design principles, adapting to specialized CAD tools, and keeping up with fast-paced project timelines. To overcome these hurdles, it's helpful to actively seek mentorship from senior engineers, engage in hands-on practice with design software, and participate in team design reviews. Embracing feedback and asking questions can accelerate learning, while staying organized helps manage multiple tasks effectively.

What are Internship SRAM Design Engineers?

Internship SRAM Design Engineers are students or recent graduates who work temporarily with engineering teams to help design, develop, and test Static Random-Access Memory (SRAM) components. They typically assist with circuit design, simulation, layout, and verification processes under the supervision of senior engineers. This role provides hands-on experience in integrated circuit (IC) design, exposure to industry-standard tools, and an understanding of the semiconductor development cycle. Interns also gain valuable insights into teamwork, problem-solving, and the application of theoretical knowledge in real-world projects.

What is the difference between Internship Sram Design Engineer vs Sram Design Engineer?

AspectInternship Sram Design EngineerSram Design Engineer
QualificationsEnrolled in or recent graduate of relevant engineering programBachelor's or Master's in Electrical/Electronic Engineering
Work EnvironmentInternship, supervised, learning-focusedFull-time, project-driven, professional setting
ResponsibilitiesAssisting in design tasks, learning industry toolsDesigning, testing, and developing SRAM components
DurationTypically 3-6 monthsFull-time, ongoing role

The main difference is that an Internship Sram Design Engineer is a temporary, learning-focused position for students or recent graduates, while a Sram Design Engineer is a full-time professional responsible for designing SRAM components. Interns gain hands-on experience, whereas full engineers lead projects and make design decisions.

What cities are hiring for Internship Sram Design Engineer jobs? Cities with the most Internship Sram Design Engineer job openings:
What are the most commonly searched types of Sram Design Engineer jobs? The most popular types of Sram Design Engineer jobs are:
What states have the most Internship Sram Design Engineer jobs? States with the most job openings for Internship Sram Design Engineer jobs include:
Internship Sram Design Engineer jobs near you
Memory Circuit Design Engineer

Memory Circuit Design Engineer

Intel

Hillsboro, OR

$122.44K - $232.19K/yr

Full-time

Medical, Retirement, PTO

Posted 19 days ago

Intel rating

8.8

Company rating: 8.8 out of 10

Based on 143 frontline employees who took The Breakroom Quiz

9th of 137 rated electronics manufacturers

Job description

Job Details:Job Description: 

You will be partnering with and leveraging domain experts across various areas of technology development, EDA vendors and product design teams to develop and deliver high-quality industry-leading memory technology collaterals and to drive circuit innovations that enable next generation high-performance, high-density, low-power embedded memory designs on Intel advanced CMOS process technologies.

In this position your responsibilities will include, but may not be limited to:

  • Memory pathfinding activities and power, performance and area (PPA) optimization through design technology co-optimization (DTCO) and product design enablement.

  • Memory bit-cell and complex periphery IC layout and automation.

  • Memory array/IP design, memory circuit innovation, test-chip design.

  • Pre-Si verification, post-Si validation and debugging to enable yield and parametric tracking/ramp.


The Advanced Design (AD) team is part of Intel's larger Design Technology Platform (DTP) Organization and is focused on pathfinding and development of advanced memory technology. These circuits enable best-in-class memory collateral, IP and innovative product design across all generations of Intel process technology. At Intel, DTP is one of the key pillars enabling Intel to deliver winning products in the marketplace. Your work will directly enable Intel's internal and external customers to get to the market faster with products that include high-performance, high-density, low-power memory at the leading edge of the technology curve and implemented in Intel's advanced CMOS process technologies.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

Minimum Qualifications:

Education level:

  • Master's degree OR Ph.D. in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline, including 2 years of professional experience.


Technical Experience:

  • Experience with CMOS ASIC design flow.

  • Custom digital circuit design, simulation, layout design, and verification

  • Experience with EDA tools used for analog, digital and mixed-signal circuit design.

  • Post-Si validation experience


Preferred Qualifications:

  • Master's degree in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related discipline with 4 years of experience OR Ph. D with 1-2 years of professional experience gained through either internships or full-time employment

  • Design, characterization, and verification of custom memory circuits such as SRAM, Register Files or ROM

  • Design trade-offs between power, performance, and area (PPA)

  • Design technology co-optimization (DTCO)

Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, California, Santa ClaraBusiness group:Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $122,440.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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