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Internship Rfic Design Engineer Jobs in San Jose, CA

Qualcomm

EM Design Engineer

Santa Clara, CA · On-site

$139K - $209K/yr

Engineering Group, Engineering Group > RFIC Design General Summary: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities ...

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All JobsRfic Design Engineer JobsInternship Rfic Design Engineer JobsInternship Rfic Design Engineer Jobs in San Jose, CA

Internship Rfic Design Engineer information

See San Jose, CA salary details

$15

$29

$45

How much do internship rfic design engineer jobs pay per hour?

As of Aug 3, 2026, the average hourly pay for internship rfic design engineer in San Jose, CA is $29.79, according to ZipRecruiter salary data. Most workers in this role earn between $24.23 and $33.80 per hour, depending on experience, location, and employer.

What is the difference between Internship Rfic Design Engineer vs RFIC Design Engineer?

AspectInternship RFIC Design EngineerRFIC Design Engineer
QualificationsEnrolled in or recent graduate of electrical engineering or related fieldBachelor's or master's in electrical engineering, with specialized RFIC knowledge
Work EnvironmentInternship programs, entry-level projects, supervised tasksFull-time professional role, independent project work, team collaboration
ResponsibilitiesAssisting in RFIC design tasks, learning industry tools, supporting senior engineersDesigning, testing, and optimizing RFICs for communication systems

The main difference between an Internship RFIC Design Engineer and an RFIC Design Engineer lies in experience, responsibilities, and career stage. Internships are designed for students or recent graduates gaining industry exposure, while RFIC Design Engineers are experienced professionals responsible for full project execution.

What are the most commonly searched types of Rfic Design Engineer jobs in San Jose, CA? The most popular types of Rfic Design Engineer jobs in San Jose, CA are:
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Internship Rfic Design Engineer jobs near you
Infographic showing various Internship Rfic Design Engineer job openings in San Jose, CA as of July 2026, with employment types broken down into 20% Internship, and 80% Full Time. Highlights an 100% In-person job distribution, with an average salary of $61,959 per year, or $29.8 per hour.

Senior RF Test & PCB Design Engineer

Prodapt North America

San Jose, CA • On-site

Other

Posted 4 days ago

Job description

Prodapt ASIC Services (formerly Innovative Logic) provides end-to-end SoC/ASIC, FPGA, and embedded software solutions. Their design services cover the complete lifecycle from RTL to GDSII, covering domains like 3nm node physical design, UVM verification, DFT, and silicon bring-up for 5G, AI, and IoT.

We are looking for Senior RF Test & PCB Design Engineer in San Jose, CA and its a 5 days onsite position
Roles & Responsibilities:

  • PCB Development: Lead the schematic entry, component selection, and layout routing optimization for complex RF evaluation boards using Cadence Allegro.
  • Simulation & Analysis: Perform Signal Integrity (SI) and Power Integrity (PI) simulations. Utilize Ansys HFSS for EM modeling and impedance matching to ensure optimal RF performance.
  • Hardware Bring-up: Own the board bring-up process, including debugging hardware issues and validating performance against design specifications.
  • RF Characterization: Utilize lab equipment (VNAs, Spectrum Analyzers, Signal Generators) to perform various RF measurements and verify simulation-to-measurement correlations. Implement Machine Learning (ML) techniques to analyze large datasets and identify performance trends or anomalies.
  • Cross-functional Collaboration: Work closely with RFIC Design and System Engineering teams to define board requirements and provide feedback on chip-level performance.
  • Documentation & Data Analysis: Maintain detailed design documentations and test reports for internal and external stakeholders. Collect, review and analyze test data. Requirements

MUST HAVES:

  • Extensive actual PCB and layout design experience (not just as a reviewer) using Cadence Allegro/OrCAD tool.  High speed or mmWave experience preferred.
  • Materials Knowledge: Deep understanding of PCB stack-ups, dielectric materials (e.g., Rogers, Megtron), and manufacturing constraints for high-frequency PCB designs.
  • Expertise in SI/PI and EM simulations.

Required Skills:

  • Education: BS or MS in Electrical Engineering or a related technical field.
  • Experience: 5+ years of hands-on experience in RF PCB design and hardware development.
  • Tools: Expert-level proficiency in Cadence Allegro/OrCAD and Ansys HFSS (or equivalent EM simulation tools).
  • RF Fundamentals: Strong knowledge of RF theory, including S-parameters, transmission line theory, matching networks, and de-embedding techniques.
  • Lab Expertise: Extensive experience with RF test equipment (VNAs, Spectrum Analyzers, Oscilloscopes) and high-speed probing techniques.
  • Materials Knowledge: Deep understanding of PCB stack-ups, dielectric materials (e.g., Rogers, Megtron), and manufacturing constraints for high-frequency PCB designs. Desirable Skills (Nice to Have)
  • Automation: Proficiency in Python or C# for developing automated test suites to increase characterization throughput.
  • Data Science for RF: Experience applying AI/ML models for predictive maintenance of test setups or for signal classification.
  • Wafer-Level Testing: Experience with manual or semi-automated RF probe stations for on-wafer die characterization.

Apply