Work closely with RFIC Design and System Engineering teams to define board requirements and provide feedback on chip-level performance. * Documentation & Data Analysis: Maintain detailed design ...
Work closely with RFIC Design and System Engineering teams to define board requirements and provide feedback on chip-level performance. * Documentation & Data Analysis: Maintain detailed design ...
... Design, simulate, and verify CMOS RFIC (e.g., LNA, mixer, power amplifier, and PLL) Provide ... Engineering 5+ years' experience in design of CMOS RFIC for 2G/3G/4G mobile handsets (e.g. GSM ...
... Design, simulate, and verify CMOS RFIC (e.g., LNA, mixer, power amplifier, and PLL) Provide ... Engineering 5+ years' experience in design of CMOS RFIC for 2G/3G/4G mobile handsets (e.g. GSM ...
... CMOS RFIC (e.g., LNA, mixer, power amplifier, and PLL) • Provide guidelines of floor plan and ... in Electrical Engineering • 5+ years' experience in design of CMOS RFIC for 2G/3G/4G mobile ...
... CMOS RFIC (e.g., LNA, mixer, power amplifier, and PLL) • Provide guidelines of floor plan and ... in Electrical Engineering • 5+ years' experience in design of CMOS RFIC for 2G/3G/4G mobile ...
... CMOS RFIC (e.g., LNA, mixer, power amplifier, and PLL) • Provide guidelines of floor plan and ... in Electrical Engineering • 5+ years' experience in design of CMOS RFIC for 2G/3G/4G mobile ...
... CMOS RFIC (e.g., LNA, mixer, power amplifier, and PLL) • Provide guidelines of floor plan and ... in Electrical Engineering • 5+ years' experience in design of CMOS RFIC for 2G/3G/4G mobile ...
Design, simulate, and verify CMOS RFIC (e.g., LNA, mixer, power amplifier, and PLL) Provide ... MS in Electrical Engineering 5+ years' experience in design of CMOS RFIC for 2G/3G/4G mobile ...
Design, simulate, and verify CMOS RFIC (e.g., LNA, mixer, power amplifier, and PLL) Provide ... MS in Electrical Engineering 5+ years' experience in design of CMOS RFIC for 2G/3G/4G mobile ...
CAD Electromagnetic RFIC Simulation Engineer
$184K - $324K/yr
... programming skills in languages like: Perl, Python, TCL, Shell, SKILL, C/C++, etc. Minimum Qualifications Experience in EDA Tool, CAD flow and RFIC methodology. Proficiency in at least one of Tcl ...
CAD Electromagnetic RFIC Simulation Engineer
$184K - $324K/yr
... programming skills in languages like: Perl, Python, TCL, Shell, SKILL, C/C++, etc. Minimum Qualifications Experience in EDA Tool, CAD flow and RFIC methodology. Proficiency in at least one of Tcl ...
CAD Electromagnetic RFIC Simulation Engineer
$150K - $277K/yr
... programming skills in languages like: Perl, Python, TCL, Shell, SKILL, C/C++, etc. Minimum Qualifications Experience in EDA Tool, CAD flow and RFIC methodology. Proficiency in at least one of Tcl ...
CAD Electromagnetic RFIC Simulation Engineer
$150K - $277K/yr
... programming skills in languages like: Perl, Python, TCL, Shell, SKILL, C/C++, etc. Minimum Qualifications Experience in EDA Tool, CAD flow and RFIC methodology. Proficiency in at least one of Tcl ...
Ph.D. in Electrical Engineering (or related) with 6+ years of analog/mixed-signal IC design ... RFIC design experience: LNA, mixer, PA driver, Broadband amplifiers, RF front-end modules.
Quick apply
Ph.D. in Electrical Engineering (or related) with 6+ years of analog/mixed-signal IC design ... RFIC design experience: LNA, mixer, PA driver, Broadband amplifiers, RF front-end modules.
Staff DSP Systems Design Engineer
San Jose, CA · On-site
$117K - $160K/yr
Exposure to mixed-signal or RFIC design in advanced CMOS nodes (28nm, 22nm, 16nm FD-SOI or FinFET ... engineering workflows is a genuine differentiator * Experience applying AI to technical ...
Quick apply
Staff DSP Systems Design Engineer
San Jose, CA · On-site
$117K - $160K/yr
Exposure to mixed-signal or RFIC design in advanced CMOS nodes (28nm, 22nm, 16nm FD-SOI or FinFET ... engineering workflows is a genuine differentiator * Experience applying AI to technical ...
Silicon RF IC Design Engineer - Senior/Principal
$146K - $201K/yr
Principal Silicon RF IC Design Engineer * Design market-leading RFIC and Microwave components and subsystems in Silicon technology. Main Duties and Responsibilities: * Take responsibility and ...
Silicon RF IC Design Engineer - Senior/Principal
$146K - $201K/yr
Principal Silicon RF IC Design Engineer * Design market-leading RFIC and Microwave components and subsystems in Silicon technology. Main Duties and Responsibilities: * Take responsibility and ...
Ph.D. in Electrical Engineering (or related) with 6+ years of analog/mixed-signal IC design ... RFIC design experience: LNA, mixer, PA driver, Broadband amplifiers, RF front-end modules.
Ph.D. in Electrical Engineering (or related) with 6+ years of analog/mixed-signal IC design ... RFIC design experience: LNA, mixer, PA driver, Broadband amplifiers, RF front-end modules.
Principal Engineer, RFIC
$214K - $341K/yr
... engineer that has strong background and hands-on experience on RFIC design. The candidate will be ... Design low-power and low-voltage RF and Analog circuits using advanced deep-submicron CMOS ...
Quick apply
Principal Engineer, RFIC
$214K - $341K/yr
... engineer that has strong background and hands-on experience on RFIC design. The candidate will be ... Design low-power and low-voltage RF and Analog circuits using advanced deep-submicron CMOS ...
Exposure to mixed-signal or RFIC design in advanced CMOS nodes (28nm, 22nm, 16nm FD-SOI or FinFET ... engineering workflows is a genuine differentiator * Experience applying AI to technical ...
Exposure to mixed-signal or RFIC design in advanced CMOS nodes (28nm, 22nm, 16nm FD-SOI or FinFET ... engineering workflows is a genuine differentiator * Experience applying AI to technical ...
RF Validation Engineer
Sunnyvale, CA · On-site
RF Validation Engineer (High Priority) Location: Sunnyvale, CA Client: Meta JD: Work with RF lead ... RFIC design.
RF Validation Engineer
Sunnyvale, CA · On-site
RF Validation Engineer (High Priority) Location: Sunnyvale, CA Client: Meta JD: Work with RF lead ... RFIC design.
Principal Engineer, RFIC
San Jose, CA · On-site
$214K - $341K/yr
... engineer that has strong background and hands-on experience on RFIC design. The candidate will be ... Design low-power and low-voltage RF and Analog circuits using advanced deep-submicron CMOS ...
Principal Engineer, RFIC
San Jose, CA · On-site
$214K - $341K/yr
... engineer that has strong background and hands-on experience on RFIC design. The candidate will be ... Design low-power and low-voltage RF and Analog circuits using advanced deep-submicron CMOS ...
Principal Engineer, RFIC
San Jose, CA · On-site
$214K - $341K/yr
... engineer that has strong background and hands-on experience on RFIC design. The candidate will be ... Design low-power and low-voltage RF and Analog circuits using advanced deep-submicron CMOS ...
Principal Engineer, RFIC
San Jose, CA · On-site
$214K - $341K/yr
... engineer that has strong background and hands-on experience on RFIC design. The candidate will be ... Design low-power and low-voltage RF and Analog circuits using advanced deep-submicron CMOS ...
New Graduate Engineer, Silicon Engineering
Palo Alto, CA · On-site
$155K - $210K/yr
RF/Analog IC Design * Simulate and model RFIC systems at high level and work with system architects, modem/DSP and ASIC engineers to partition functions between hardware and software domains * Derive ...
New Graduate Engineer, Silicon Engineering
Palo Alto, CA · On-site
$155K - $210K/yr
RF/Analog IC Design * Simulate and model RFIC systems at high level and work with system architects, modem/DSP and ASIC engineers to partition functions between hardware and software domains * Derive ...
RFIC Layout Engineer
San Francisco, CA · On-site
To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and ... Description As an RFIC Layout Engineer, you will be a key member of a RFIC team, researching ...
RFIC Layout Engineer
San Francisco, CA · On-site
To deliver these radios, our team is responsible for the design of a wide range of RF, analog, and ... Description As an RFIC Layout Engineer, you will be a key member of a RFIC team, researching ...
New Graduate Engineer, Silicon Engineering
Palo Alto, CA · On-site
$135 - $210/hr
RF/Analog IC Design * Simulate and model RFIC systems at high level and work with system architects, modem/DSP and ASIC engineers to partition functions between hardware and software domains * Derive ...
New
New Graduate Engineer, Silicon Engineering
Palo Alto, CA · On-site
$135 - $210/hr
RF/Analog IC Design * Simulate and model RFIC systems at high level and work with system architects, modem/DSP and ASIC engineers to partition functions between hardware and software domains * Derive ...
New
RFIC Layout Designer (RFIC Engineering)
$130K - $185K/yr
We design, build, test, and operate all parts of the system - thousands of satellites, consumer ... engineer to determine pad locations * Accurately estimate the schedule for the layout work and ...
RFIC Layout Designer (RFIC Engineering)
$130K - $185K/yr
We design, build, test, and operate all parts of the system - thousands of satellites, consumer ... engineer to determine pad locations * Accurately estimate the schedule for the layout work and ...
Internship Rfic Design Engineer information
See Palo Alto, CA salary details
$15.82 - $18.52
5% of jobs
$18.52 - $21.22
7% of jobs
$23.86 is the 25th percentile. Wages below this are outliers.
$21.22 - $23.92
13% of jobs
$23.92 - $26.61
9% of jobs
The median wage is $28.79 / hr.
$26.61 - $29.31
19% of jobs
$29.31 - $32.01
18% of jobs
$32.68 is the 75th percentile. Wages above this are outliers.
$32.01 - $34.71
14% of jobs
$34.71 - $37.40
7% of jobs
$37.40 - $40.10
4% of jobs
$40.10 - $42.80
0% of jobs
$42.80 - $45.50
3% of jobs
$15
$29
$45
How much do internship rfic design engineer jobs pay per hour?
As of Aug 19, 2026, the average hourly pay for internship rfic design engineer in Palo Alto, CA is $29.88, according to ZipRecruiter salary data. Most workers in this role earn between $24.28 and $33.89 per hour, depending on experience, location, and employer.
What is the difference between Internship Rfic Design Engineer vs RFIC Design Engineer?
| Aspect | Internship RFIC Design Engineer | RFIC Design Engineer |
|---|---|---|
| Qualifications | Enrolled in or recent graduate of electrical engineering or related field | Bachelor's or master's in electrical engineering, with specialized RFIC knowledge |
| Work Environment | Internship programs, entry-level projects, supervised tasks | Full-time professional role, independent project work, team collaboration |
| Responsibilities | Assisting in RFIC design tasks, learning industry tools, supporting senior engineers | Designing, testing, and optimizing RFICs for communication systems |
The main difference between an Internship RFIC Design Engineer and an RFIC Design Engineer lies in experience, responsibilities, and career stage. Internships are designed for students or recent graduates gaining industry exposure, while RFIC Design Engineers are experienced professionals responsible for full project execution.
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Cities near Palo Alto, CA with the most Internship Rfic Design Engineer job openings:
Other
Re-posted 22 days ago
Job description
Duration: 12+ months contract
Location: San Jose, CA (Onsite, 5 days/week)
Description:
- PCB Development: Lead the schematic entry, component selection, and layout routing optimization for complex RF evaluation boards using Cadence Allegro.
- Simulation & Analysis: Perform Signal Integrity (SI) and Power Integrity (PI) simulations. Utilize Ansys HFSS for EM modeling and impedance matching to ensure optimal RF performance.
- Hardware Bring-up: Own the board bring-up process, including debugging hardware issues and validating performance against design specifications.
- RF Characterization: Utilize lab equipment (VNAs, Spectrum Analyzers, Signal Generators) to perform various RF measurements and verify simulation-to-measurement correlations. Implement Machine Learning (ML) techniques to analyze large datasets and identify performance trends or anomalies.
- Cross-functional Collaboration: Work closely with RFIC Design and System Engineering teams to define board requirements and provide feedback on chip-level performance.
- Documentation & Data Analysis: Maintain detailed design documentations and test reports for internal and external stakeholders. Collect, review and analyze test data.
Required Skills & Qualifications:
- Education: BS or MS in Electrical Engineering or a related technical field.
- Experience: 5+ years of hands-on experience in RF PCB design and hardware development.
- Tools: Expert-level proficiency in Cadence Allegro/OrCAD and Ansys HFSS (or equivalent EM simulation tools).
- RF Fundamentals: Strong knowledge of RF theory, including S-parameters, transmission line theory, matching networks, and de-embedding techniques.
- Lab Expertise: Extensive experience with RF test equipment (VNAs, Spectrum Analyzers, Oscilloscopes) and high-speed probing techniques.
- Materials Knowledge: Deep understanding of PCB stack-ups, dielectric materials (e.g., Rogers, Megtron), and manufacturing constraints for high-frequency PCB designs.
Desirable Skills (Nice to Have)
- Automation: Proficiency in Python or C# for developing automated test suites to increase characterization throughput.
- Data Science for RF: Experience applying AI/ML models for predictive maintenance of test setups or for signal classification.
- Wafer-Level Testing: Experience with manual or semi-automated RF probe stations for on-wafer die characterization.
About Xoriant
Sourced by ZipRecruiter
Industry
It services
Company size
1,001 - 5,000 Employees
Headquarters location
Sunnyvale, CA, US
Year founded
1990