ZipRecruiter

Log In

1

Internship Rfic Design Engineer Jobs in Palo Alto, CA

Tacit

RFIC Silicon Lead

San Francisco, CA · On-site

$180K - $230K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

MS or PhD in electrical engineering, or equivalent experience * 10+ years in RFIC design, with substantial industry experience delivering silicon * Deep experience in low-power CMOS RF, synthesizers ...

Western Digital

Senior Principal RFIC Design Engineer

San Jose, CA · On-site

$147K - $202K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

We combine deep engineering expertise with global-scale manufacturing to deliver the storage ... Designer will be responsible for the design of high performance RF and analog circuit blocks.

Qualcomm

RF/Analog IC Design Engineer

Santa Clara, CA · On-site

Engineering Group, Engineering Group > RFIC Design General Summary: Define, design and develop ... D. in Electrical Engineering with internship or publication. • 5+ years of experience in one or ...

Entrada Ventures

Head of Engineering (RFIC Focus)

Mountain View, CA · On-site

$160 - $210/hr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

The Role We are hiring a Head of Engineering to lead our engineering organization through its next ... Hands‑On RFIC Design : Design, simulate, layout, and integrate front‑end circuits (LNAs, PAs ...

Western Digital

Senior Principal RFIC Design Engineer

San Jose, CA · On-site

$147K - $202K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

We combine deep engineering expertise with global-scale manufacturing to deliver the storage ... Designer will be responsible for the design of high performance RF and analog circuit blocks.

Qualcomm

EM Design Engineer

Santa Clara, CA · On-site

$139K - $209K/yr

Engineering Group, Engineering Group > RFIC Design General Summary: Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities ...

previous pagenext page

Showing results 21-40

All JobsRfic Design Engineer JobsInternship Rfic Design Engineer JobsInternship Rfic Design Engineer Jobs in Palo Alto, CA

Internship Rfic Design Engineer information

See Palo Alto, CA salary details

$15

$29

$45

How much do internship rfic design engineer jobs pay per hour?

As of Aug 19, 2026, the average hourly pay for internship rfic design engineer in Palo Alto, CA is $29.88, according to ZipRecruiter salary data. Most workers in this role earn between $24.28 and $33.89 per hour, depending on experience, location, and employer.

What is the difference between Internship Rfic Design Engineer vs RFIC Design Engineer?

AspectInternship RFIC Design EngineerRFIC Design Engineer
QualificationsEnrolled in or recent graduate of electrical engineering or related fieldBachelor's or master's in electrical engineering, with specialized RFIC knowledge
Work EnvironmentInternship programs, entry-level projects, supervised tasksFull-time professional role, independent project work, team collaboration
ResponsibilitiesAssisting in RFIC design tasks, learning industry tools, supporting senior engineersDesigning, testing, and optimizing RFICs for communication systems

The main difference between an Internship RFIC Design Engineer and an RFIC Design Engineer lies in experience, responsibilities, and career stage. Internships are designed for students or recent graduates gaining industry exposure, while RFIC Design Engineers are experienced professionals responsible for full project execution.

What are popular job titles related to Internship Rfic Design Engineer jobs in Palo Alto, CA?

For Internship Rfic Design Engineer jobs in Palo Alto, CA, the most frequently searched job titles are:

What job categories do people searching Internship Rfic Design Engineer jobs in Palo Alto, CA look for?

The top searched job categories for Internship Rfic Design Engineer jobs in Palo Alto, CA are:

What cities near Palo Alto, CA are hiring for Internship Rfic Design Engineer jobs?

Cities near Palo Alto, CA with the most Internship Rfic Design Engineer job openings:

Internship Rfic Design Engineer jobs near you
Infographic showing various Internship Rfic Design Engineer job openings in Palo Alto, CA as of August 2026, with employment types broken down into 83% Full Time, 13% Part Time, and 4% Contract. Highlights an 82% Physical, 5% Hybrid, and 13% Remote job distribution, with an average salary of $62,146 per year, or $29.9 per hour.

RFIC Silicon Lead

Tacit

San Francisco, CA • On-site

$180K - $230K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Re-posted 27 days ago

Job description

About Tacit
We are an early-stage, deep tech startup based in San Francisco, developing innovative hardware that rethinks human-computer interaction. We are backed by General Catalyst, Khosla Ventures, and Greylock Partners, with a founding team from Stanford, BrainGate, Oculus, and Tesla. While we can't reveal too much just yet, our team is tackling cutting-edge engineering challenges to bring revolutionary products to life.
About the role
We are building CMOS RF systems at ultra low-power envelopes. We are looking for our first silicon hire: the person who will define the RF CMOS architecture, translate Tacit's sensing and ML constraints into circuit reality, and set the technical foundation for everything that follows.
This role starts hands-on. You will work at the transistor level, stand up the initial design environment, evaluate process options, simulate and design critical blocks, and drive early silicon decisions. But the most important responsibility is architectural judgment: determining what RF front-end, synthesizer, power-management, and duty-cycling approaches can actually close in CMOS at our target power envelopes.
The rare skill we are looking for is not generic RFIC execution. It is the ability to reason across system architecture, low-power CMOS RF, frequency generation, sensing constraints, form factor, and product requirements - and to know when a proposed path will or will not work in silicon.
As the program matures, you will help decide what stays internal and what is executed with external silicon partners. You may directly own blocks, technically direct contractors, or build the internal team. In all cases, the architecture-defining IP and technical judgment must live inside Tacit.
What you'll do
  • Define the RF CMOS architecture for an ultra-low-power, frequency-agile sensing front end
  • Translate system-level sensing, ML, and form-factor constraints into circuit-level requirements
  • Design and/or technically direct critical RF circuit blocks, including VCOs, PLLs, mixers, LNAs, buffers, passives, clocking, biasing, and power-management structures
  • Architect fast-settling frequency generation and hopping approaches suitable for aggressive duty-cycled operation
  • Drive power-reduction methodology across the RF system: duty-cycle co-design, supply gating, bias trimming, wake/sleep transients, and system-level power tradeoffs
  • Evaluate and recommend CMOS process options for a low-power wideband / frequency-agile SoC, including tradeoffs across 28nm, 22FDX, 55nm RF, and related nodes
  • Stand up and operate the early RFIC design environment, including Cadence Virtuoso, Spectre, ADE, EM simulation, Calibre, and PDK flows
  • Identify when an architecture will not close in silicon, and propose practical relaxations or alternatives
  • Own or technically direct implementation through DRC/LVS, tape-out, packaging, bring-up, measurement correlation, and iteration
  • Evaluate, select, and technically manage external silicon partners where appropriate, while keeping architecture-defining IP and technical judgment inside Tacit
  • Help build the future silicon team as the architecture, program, and company scale
Requirements
  • MS or PhD in electrical engineering, or equivalent experience
  • 10+ years in RFIC design, with substantial industry experience delivering silicon
  • Deep experience in low-power CMOS RF, synthesizers, radar, UWB, frequency-agile radios, or related sensing systems
  • Strong transistor-level design ability in Cadence Virtuoso, Spectre, and ADE
  • Expertise in synthesizer and RF front-end circuits, especially VCOs, PLLs, mixers, LNAs, buffers, passives, clocking, and biasing
  • Strong understanding of CMOS process tradeoffs, device behavior, stack selection, parasitics, layout effects, and RF process-node selection
  • Experience with EM simulation tools such as EMX, HFSS, Momentum, or equivalent
  • Track record taking RFIC blocks or systems from architecture through silicon validation
  • Ability to reason across architecture, circuits, layout, packaging, measurement, power, and product constraints
  • Ability to translate ambiguous system-level goals into concrete circuit and silicon tradeoffs
  • Strong communication skills and ability to lead technical decisions in a small, fast-moving team
Strong candidates may have
  • Background in low-power radar, UWB, frequency synthesizers, or frequency-agile sensing front ends
  • Experience with fast-settling PLLs, wideband frequency generation, duty-cycled RF systems, or ultra-low-power sensing radios
  • Experience with 28nm, 22FDX, 55nm RF, or other RF-capable CMOS processes
  • Experience as a first or early silicon hire at a startup
  • Experience managing external design houses, foundries, packaging vendors, or semiconductor supply-chain partners
  • Experience with RF/analog/digital co-design and system-level power optimization
  • Experience building, hiring, or mentoring RFIC teams
  • Strategic mindset: engineering decisions framed in terms of business outcomes, product milestones, defensible IP, and time-to-market

Compensation Range
$180,000 - $230,000/year plus meaningful equity package
Benefits
  • Competitive equity package
  • Comprehensive medical, dental, and vision insurance
  • Company size: 30-50 people
  • Unlimited PTO
  • Visa sponsorship
  • 4% 401k matching

Apply