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Internship Ic Layout Design Engineer Jobs in Virginia

Fractile

Physical Design Engineer

Bristol, VA · On-site

$80 - $120/hr

As a Physical Design Engineer, you will support the implementation of complex IC physical designs ... Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification ...

Hirekeyz Inc

Mechanical Design Engineer

Richmond, VA · On-site

$75K - $101K/yr

Proven experience in LV switchgear design, panel layout, and busbar layout. * Good understanding of UL standards, specifically UL891 and UL1558. * Familiarity with engineering design review and ...

Cystems Logic Inc

Mechanical Design Engineer

Richmond, VA · On-site

$75K - $101K/yr

Proven experience in LV switchgear design, panel layout, and busbar layout. Good understanding of UL standards, specifically UL891 and UL1558. Familiarity with engineering design review and design ...

Fractile

Lead Physical Design Engineer

Bristol, VA · On-site

$120 - $180/hr

... IC physical designs, from synthesis to sign-off. In this role, you will take on leadership ... Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification ...

Mu-Del Electronics

Be Seen First

PCB Design Engineer

Manassas, VA · On-site

Position Overview Mu-Del Electronics is seeking a highly skilled PCB Design Engineer with strong ... Perform schematic capture, PCB layout, and signal integrity analysis using Altium * Develop high ...

Thompson & Litton Inc

Civil Design Engineer

Radford, VA · On-site

$63K - $79K/yr

You will: * Infrastructure & Site Design: Assist in the design and layout of municipal ... Any academic coursework, internships, or prior work experience in water and wastewater systems is ...

Power Monitors, Inc.

Electronic Design Engineer

VA · On-site

$65K - $130K/yr

Embedded Hardware Design Engineer Location: Mount Crawford, VA (Shenandoah Valley) Company: Power ... Experience with schematic capture and PCB layout tools * Analog signal conditioning and/or ...

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Internship Ic Layout Design Engineer information

What is the difference between Internship Ic Layout Design Engineer vs IC Design Engineer?

AspectInternship IC Layout Design EngineerIC Design Engineer
CredentialsTypically pursuing or recently completed relevant degree; internship experienceBachelor's or Master's in Electrical/Electronic Engineering; professional experience preferred
Work EnvironmentInternship programs, entry-level tasks, supervised environmentFull-time professional role, independent project work, team collaboration
ResponsibilitiesAssisting in layout design, learning design tools, supporting senior engineersDesigning, simulating, and verifying integrated circuit layouts independently

In summary, an Internship IC Layout Design Engineer is a trainee gaining hands-on experience under supervision, while an IC Design Engineer is a full-time professional responsible for designing and verifying integrated circuits independently.

What cities in Virginia are hiring for Internship Ic Layout Design Engineer jobs? Cities in Virginia with the most Internship Ic Layout Design Engineer job openings:
Internship Ic Layout Design Engineer jobs near you

Physical Design Engineer

Fractile

Bristol, VA • On-site

$80 - $120/hr

Other

Posted 4 days ago

Job description

Fractile’s mission is to enable a new chapter in the AI revolution. We’re pioneering AI innovation where hardware and software join to create something extraordinary, unlocking the power of the world’s largest language models with speed increases of x100. Our team is rapidly expanding, and we're searching for visionary engineers, scientists, and thinkers who share our passion for pushing boundaries and redefining what's possible. If you're ready to join a dynamic group of innovators shaping AI's future, we want to hear from you!

We are seeking a Physical Design Engineer to contribute to our next‑generation chip designs. As a Physical Design Engineer, you will support the implementation of complex IC physical designs, from synthesis to sign‑off. You will collaborate with cross‑functional teams, including logic design, verification, and process technology, to optimise performance, power, and area (PPA) while ensuring design integrity and manufacturability.

Key Responsibilities:
  • Support the physical implementation of ASIC/SoC designs, including floor planning, placement, clock tree synthesis (CTS), routing, and sign‑off.
  • Work on synthesis, timing analysis (STA), and optimisation to achieve strong PPA metrics.
  • Assist in power planning and analysis, addressing IR drop, electromigration, and related effects.
  • Ensure design rule check (DRC), layout vs. schematic (LVS), and other physical verification compliance.
  • Collaborate with DFT engineers to integrate design‑for‑test (DFT) structures into the physical implementation.
  • Develop flows in EDA tools such as Cadence Innovus, Synopsys Fusion Compiler, Mentor Graphics Calibre, and others.
  • Work closely with RTL and architecture teams to support design feasibility, constraints, and physical‑aware RTL design.
  • Work with advanced AI tools and models to improve productivity, analysis, and design quality.
Preferred Qualifications:
  • Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
  • 0–5 years of experience in physical design for advanced technology nodes (e.g., 7nm, 5nm, or below), including internships.
  • Familiarity with EDA tools for place & route, STA, and sign‑off.
  • Basic understanding of CMOS technology, semiconductor physics, and process limitations.
  • Exposure to timing closure, signal integrity, IR drop analysis, and formal verification.
  • Proficiency in scripting languages like TCL, Perl, or Python for automation is a plus.
  • Excellent problem‑solving skills, communication, and teamwork in a collaborative design environment.
  • Interest in working with advanced AI tools and models as part of the design workflow.
  • Experience or coursework in high‑performance computing (HPC), AI accelerators, or networking chips is a plus.
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