Principal RTL Design Engineer
Boise, ID · On-site
In Custom Solutions, you'll collaborate with elite engineering teams across disciplines-from ... Ensure design correctness through lint, CDC, RDC, and peer reviews * Collaborate with verification ...
Principal RTL Design Engineer
Boise, ID · On-site
In Custom Solutions, you'll collaborate with elite engineering teams across disciplines-from ... Ensure design correctness through lint, CDC, RDC, and peer reviews * Collaborate with verification ...
... CDC at the chip level. * Lead design effort for internally developed processor IP blocks to meet ... Bachelor's degree in Electrical engineering, Electronics, Computer engineering, or related ...
... CDC at the chip level. * Lead design effort for internally developed processor IP blocks to meet ... Bachelor's degree in Electrical engineering, Electronics, Computer engineering, or related ...
... CDC at the chip level. * Lead design effort for internally developed processor IP blocks to meet ... Bachelor's degree in Electrical engineering, Electronics, Computer engineering, or related fields ...
... CDC at the chip level. * Lead design effort for internally developed processor IP blocks to meet ... Bachelor's degree in Electrical engineering, Electronics, Computer engineering, or related fields ...
... check, CDC check, Lint check, power analysis, design review, silicon debugging, design ... Engineering, Computer Science, or similar field with 10+ years of experience on digital IC design ...
... check, CDC check, Lint check, power analysis, design review, silicon debugging, design ... Engineering, Computer Science, or similar field with 10+ years of experience on digital IC design ...
... CDC check, Lint check,power analysis, design review, silicon debugging, design documentation and ... Engineering, Computer Science, or similar field with 10+ years of experience on digital IC design ...
... CDC check, Lint check,power analysis, design review, silicon debugging, design documentation and ... Engineering, Computer Science, or similar field with 10+ years of experience on digital IC design ...
Intern, R&D (Fall 2026 - Summer 2027)
Tampa, FL · On-site
$20/hr
Requirements of the R&D Internship * Currently enrolled in an undergraduate or graduate Engineering ... CDC guidance. Axogen reserves the right to amend its policies from time to time in its sole ...
Intern, R&D (Fall 2026 - Summer 2027)
Tampa, FL · On-site
$20/hr
Requirements of the R&D Internship * Currently enrolled in an undergraduate or graduate Engineering ... CDC guidance. Axogen reserves the right to amend its policies from time to time in its sole ...
Requirements of the R&D Internship * Currently enrolled in an undergraduate or graduate Engineering ... CDC guidance. Axogen reserves the right to amend its policies from time to time in its sole ...
Quick apply
Requirements of the R&D Internship * Currently enrolled in an undergraduate or graduate Engineering ... CDC guidance. Axogen reserves the right to amend its policies from time to time in its sole ...
Join Micron's Memory Systems Engineering team and contribute to the development of premier digital ... Collaborate with design verification teams to support verification planning, coverage goals, CDC ...
Join Micron's Memory Systems Engineering team and contribute to the development of premier digital ... Collaborate with design verification teams to support verification planning, coverage goals, CDC ...
Join Micron's Memory Systems Engineering team and contribute to the development of premier digital ... Collaborate with design verification teams to support verification planning, coverage goals, CDC ...
Join Micron's Memory Systems Engineering team and contribute to the development of premier digital ... Collaborate with design verification teams to support verification planning, coverage goals, CDC ...
... CDC at the chip level. * Lead design effort for internally developed processor IP blocks to meet ... Bachelor's degree in Computer Engineering, Electrical Engineering or related fields and 5+ years of ...
... CDC at the chip level. * Lead design effort for internally developed processor IP blocks to meet ... Bachelor's degree in Computer Engineering, Electrical Engineering or related fields and 5+ years of ...
... CDC at the chip level. * Lead design effort for internally developed processor IP blocks to meet ... Bachelor's degree in Computer Engineering, Electrical Engineering or related fields and 5+ years of ...
... CDC at the chip level. * Lead design effort for internally developed processor IP blocks to meet ... Bachelor's degree in Computer Engineering, Electrical Engineering or related fields and 5+ years of ...
... CDC at the chip level. * Lead design effort for internally developed processor IP blocks to meet ... Bachelor's degree in Computer Engineering, Electrical Engineering or related fields and 5+ years of ...
... CDC at the chip level. * Lead design effort for internally developed processor IP blocks to meet ... Bachelor's degree in Computer Engineering, Electrical Engineering or related fields and 5+ years of ...
... CDC at the chip level. * Lead design effort for internally developed processor IP blocks to meet ... Bachelor's degree in Computer Engineering, Electrical Engineering or related fields and 5+ years of ...
... CDC at the chip level. * Lead design effort for internally developed processor IP blocks to meet ... Bachelor's degree in Computer Engineering, Electrical Engineering or related fields and 5+ years of ...
... CDC at the chip level. * Lead design effort for internally developed processor IP blocks to meet ... Bachelor's degree in Computer Engineering, Electrical Engineering or related fields and 5+ years of ...
... CDC at the chip level. * Lead design effort for internally developed processor IP blocks to meet ... Bachelor's degree in Computer Engineering, Electrical Engineering or related fields and 5+ years of ...
... CDC at the chip level. * Lead design effort for internally developed processor IP blocks to meet ... Bachelor's degree in Computer Engineering, Electrical Engineering or related fields and 5+ years of ...
... CDC at the chip level. * Lead design effort for internally developed processor IP blocks to meet ... Bachelor's degree in Computer Engineering, Electrical Engineering or related fields and 5+ years of ...
... engineering. We intend to be the world's best and most reliable database, built by an excellent ... BASIC QUALIFICATIONS - 3+ years of non-internship professional software development experience - 2+ ...
... engineering. We intend to be the world's best and most reliable database, built by an excellent ... BASIC QUALIFICATIONS - 3+ years of non-internship professional software development experience - 2+ ...
... engineering. We intend to be the world's best and most reliable database, built by an excellent ... BASIC QUALIFICATIONS - 3+ years of non-internship professional software development experience - 2+ ...
... engineering. We intend to be the world's best and most reliable database, built by an excellent ... BASIC QUALIFICATIONS - 3+ years of non-internship professional software development experience - 2+ ...
... engineering. We intend to be the world's best and most reliable database, built by an excellent ... BASIC QUALIFICATIONS - 3+ years of non-internship professional software development experience - 2+ ...
... engineering. We intend to be the world's best and most reliable database, built by an excellent ... BASIC QUALIFICATIONS - 3+ years of non-internship professional software development experience - 2+ ...
Mixed Signal Logic Design Engineer
Folsom, CA · On-site
$122K - $232K/yr
Experience with Front End design tools for Lint, CDC, RDC, Voltage Domain Crossings, Synthesis, Low ... The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable ...
Mixed Signal Logic Design Engineer
Folsom, CA · On-site
$122K - $232K/yr
Experience with Front End design tools for Lint, CDC, RDC, Voltage Domain Crossings, Synthesis, Low ... The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable ...
Mixed Signal Logic Design Engineer
$122K - $232K/yr
Experience with Front End design tools for Lint, CDC, RDC, Voltage Domain Crossings, Synthesis, Low ... The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable ...
Mixed Signal Logic Design Engineer
$122K - $232K/yr
Experience with Front End design tools for Lint, CDC, RDC, Voltage Domain Crossings, Synthesis, Low ... The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable ...
Internship Cdc Engineering information
See salary details
$11.06 - $12.74
2% of jobs
$12.74 - $14.42
4% of jobs
$16.11 is the 25th percentile. Wages below this are outliers.
$14.42 - $16.11
19% of jobs
$16.11 - $17.79
24% of jobs
The median wage is $17.89 / hr.
$17.79 - $19.47
17% of jobs
$20.48 is the 75th percentile. Wages above this are outliers.
$19.47 - $21.15
16% of jobs
$21.15 - $22.84
6% of jobs
$22.84 - $24.52
5% of jobs
$24.52 - $26.20
3% of jobs
$26.20 - $27.88
3% of jobs
$27.88 - $29.57
1% of jobs
$11
$19
$29
How much do internship cdc engineering jobs pay per hour?
As of Jul 3, 2026, the average hourly pay for internship cdc engineering in the United States is $19.31, according to ZipRecruiter salary data. Most workers in this role earn between $16.11 and $20.91 per hour, depending on experience, location, and employer.
What is the difference between Internship Cdc Engineering vs Civil Engineering Intern?
| Aspect | Internship Cdc Engineering | Civil Engineering Intern |
|---|---|---|
| Required Credentials | Typically pursuing or recent graduate in civil engineering or related field | Same as CDC Engineering internship, often requiring enrollment in civil engineering program |
| Work Environment | Construction sites, engineering offices, project sites | Construction sites, design offices, fieldwork environments |
| Employer & Industry Usage | Government agencies, construction firms, infrastructure projects | Engineering firms, government departments, infrastructure projects |
Both internships focus on civil engineering principles, site work, and project support. The main difference lies in the specific focus areas: CDC Engineering internships often emphasize public health infrastructure and specialized projects, while Civil Engineering Internships cover a broader range of civil projects. Both roles provide valuable hands-on experience in construction and design environments.
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What cities are hiring for Internship Cdc Engineering jobs? Cities with the most Internship Cdc Engineering job openings:
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Full-time
Life, Retirement
Posted 21 days ago
Job description
About Marvell
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Marvell Custom Solutions partners with the world's most advanced technology companies-including leading hyperscalers, cloud data center operators, and telecom providers-to architect and deliver next-generation custom silicon that powers AI infrastructure, cloud computing, and 5G networks. Our team drives innovation at the forefront of semiconductor design, working on cutting-edge System-on-Chips (SoCs) built in the most advanced process nodes (3nm, 2nm) that leverage best-in-class IP portfolios spanning high-speed SerDes (112G+), advanced die-to-die interconnects, custom HBM memory architectures, PCIe Gen 6/7, and CXL 3.0 technologies-all integrated using breakthrough advanced packaging techniques including 2.5D, 3D, and co-packaged optics.
In Custom Solutions, you'll collaborate with elite engineering teams across disciplines-from architecture and design through validation and production-to solve complex technical challenges that directly impact how billions of people experience technology, ensuring that every design meets the exacting specifications and performance requirements that our customers depend on to power their mission-critical infrastructure.
What You Can Expect
As a Principal Design Engineer, you will lead micro-architecture and RTL development and HW/SW co-design efforts working across multi-functional teams, in developing state-of-the-art designs.
What We're Looking For
To be successful in this role, you must:
Expected Base Pay Range (USD)
160,400 - 237,320, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
#LI-JT2
Marvell's semiconductor solutions are the essential building blocks of the data infrastructure that connects our world. Across enterprise, cloud and AI, and carrier architectures, our innovative technology is enabling new possibilities.
At Marvell, you can affect the arc of individual lives, lift the trajectory of entire industries, and fuel the transformative potential of tomorrow. For those looking to make their mark on purposeful and enduring innovation, above and beyond fleeting trends, Marvell is a place to thrive, learn, and lead.
Your Team, Your Impact
Marvell Custom Solutions partners with the world's most advanced technology companies-including leading hyperscalers, cloud data center operators, and telecom providers-to architect and deliver next-generation custom silicon that powers AI infrastructure, cloud computing, and 5G networks. Our team drives innovation at the forefront of semiconductor design, working on cutting-edge System-on-Chips (SoCs) built in the most advanced process nodes (3nm, 2nm) that leverage best-in-class IP portfolios spanning high-speed SerDes (112G+), advanced die-to-die interconnects, custom HBM memory architectures, PCIe Gen 6/7, and CXL 3.0 technologies-all integrated using breakthrough advanced packaging techniques including 2.5D, 3D, and co-packaged optics.
In Custom Solutions, you'll collaborate with elite engineering teams across disciplines-from architecture and design through validation and production-to solve complex technical challenges that directly impact how billions of people experience technology, ensuring that every design meets the exacting specifications and performance requirements that our customers depend on to power their mission-critical infrastructure.
What You Can Expect
As a Principal Design Engineer, you will lead micro-architecture and RTL development and HW/SW co-design efforts working across multi-functional teams, in developing state-of-the-art designs.
- Own RTL design, implementation, and integration of complex blocks or subsystems
- Define and influence block-level and subsystem-level micro-architecture
- Develop high-quality, synthesizable RTL using Verilog/SystemVerilog
- Ensure design correctness through lint, CDC, RDC, and peer reviews
- Collaborate with verification, validation, Firmware and synthesis/STA, and physical design teams
- Identify and resolve complex functional, timing, power and integration issues
- Contribute to digital design methodologies and best practices
- Mentor and guide junior engineers
- Lead design and tape-out readiness reviews
What We're Looking For
To be successful in this role, you must:
- Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field
- 12+ years of experience in digital IC or SoC RTL design
- Deep expertise in RTL using System Verilog design and micro-architecture
- Strong understanding of clocking, reset, and power-aware design, SoC architecture, processor cores, memory, peripheral interfaces through hand on prior experience
- Hands-on experience with lint, CDC, and RDC analysis
- Proven ownership and track record of block or subsystem delivery on production silicon with aggressive development schedules.
- Strong debugging and problem-solving skills and multi-tasking
- Hands on experience in scripting language such as Perl/Python.
- Familiarity with low-power design techniques
- Exposure to synthesis, STA, or physical design flows
- Experience mentoring engineers or leading technical reviews
Expected Base Pay Range (USD)
160,400 - 237,320, $ per annum
The successful candidate's starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions. The expected base pay range for this role may be modified based on market conditions.
Additional Compensation and Benefit Elements
Marvell is committed to providing exceptional, comprehensive benefits that support our employees at every stage - from internship to retirement and through life's most important moments. Our offerings are built around four key pillars: financial well-being, family support, mental and physical health, and recognition. Highlights include an employee stock purchase plan with a 2-year look back, family support programs to help balance work and home life, robust mental health resources to prioritize emotional well-being, and a recognition and service awards to celebrate contributions and milestones. We look forward to sharing more with you during the interview process.
All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, national origin, sexual orientation, gender identity, disability or protected veteran status.
Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at TAOps@marvell.com.
Interview Integrity
To support fair and authentic hiring practices, candidates are not permitted to use AI tools (such as transcription apps, real-time answer generators like ChatGPT or Copilot, or automated note-taking bots) during interviews.
These tools must not be used to record, assist with, or enhance responses in any way. Our interviews are designed to evaluate your individual experience, thought process, and communication skills in real time. Use of AI tools without prior instruction from the interviewer will result in disqualification from the hiring process.
This position may require access to technology and/or software subject to U.S. export control laws and regulations, including the Export Administration Regulations (EAR). As such, applicants must be eligible to access export-controlled information as defined under applicable law. Marvell may be required to obtain export licensing approval from the U.S. Department of Commerce and/or the U.S. Department of State. Except for U.S. citizens, lawful permanent residents, or protected individuals as defined by 8 U.S.C. 1324b(a)(3), all applicants may be subject to an export license review process prior to employment.
#LI-JT2
About Marvell
Sourced by ZipRecruiter
Industry
Manufacturing
Company size
10,000+ Employees
Headquarters location
Santa Clara, CA, US
Year founded
1995