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Internship Asic Rtl Design Engineer Jobs in Ontario, CA

Phizenix

Digital Design Engineer

Irvine, CA · On-site

$180K - $250K/yr

Strong fundamentals in digital ASIC design, micro-architecture, and best RTL coding methods. * Firmware / embedded C development, including bare-metal programming on an on-chip RISC CPU IP (e.g ...

Apple

DDR Design Engineer

Irvine, CA · On-site

As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...

SpaceX

New Graduate Engineer, Silicon Engineering

Irvine, CA · On-site

$145K - $195K/yr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

NEW GRADUATE ENGINEER, SILICON ENGINEERING Are you an engineering student graduating in fall or ... ASIC/FPGA design and verification flows * Contribute towards design architecture, RTL ...

New

Apple

DDR Design Engineer

Irvine, CA · On-site

As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...

Marvell Technology, Inc.

Digital Design Engineer

Irvine, CA · On-site

$146K/yr

  • Life

  • Retirement

Develop ASIC specification, architecture, and micro-architecture of major functional blocks in ... Development/simulation of RTL hardware implementations in Verilog and System Verilog * Document and ...

Marvell

Digital Design Engineer

Irvine, CA · On-site

$146K/yr

  • Life

  • Retirement

Develop ASIC specification, architecture, and micro-architecture of major functional blocks in ... Development/simulation of RTL hardware implementations in Verilog and System Verilog * Document and ...

Marvell

Senior Staff Digital Design Engineer

Irvine, CA · On-site

  • Life

  • Retirement

Extensive experience in digital ASIC design , including microarchitecture development, RTL ... every stage - from internship to retirement and through life's most important moments. Our ...

Apple

DDR Design Engineer

Irvine, CA

$122K - $214K/yr

  • Medical

  • Dental

  • Retirement

You will provide high-quality RTL description, including assertions, for the design. Use formal ... Electrical Engineering. Pay & Benefits At Apple, base pay is one part of our total compensation ...

Apple

DDR Design Engineer

Irvine, CA

$175K - $308K/yr

  • Medical

  • Dental

  • Retirement

As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...

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Showing results 21-40

All JobsAsic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer Jobs in Ontario, CA

Internship Asic Rtl Design Engineer information

See Ontario, CA salary details

$95.6K

$152.8K

$205.5K

How much do internship asic rtl design engineer jobs pay per year?

As of Aug 18, 2026, the average yearly pay for internship asic rtl design engineer in Ontario, CA is $152,815.00, according to ZipRecruiter salary data. Most workers in this role earn between $133,800.00 and $183,100.00 per year, depending on experience, location, and employer.

What is an internship ASIC RTL design engineer?

An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.

What does an internship ASIC RTL design engineer do?

As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.

What are the key skills and qualifications needed to thrive as an internship ASIC RTL design engineer?

To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.

What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?

AspectInternship Asic Rtl Design EngineerAsic Verification Engineer
CredentialsTypically pursuing or recently completed a degree in Electrical Engineering or Computer EngineeringSimilar educational background, often with additional coursework in verification methodologies
Work EnvironmentInternship setting, supervised, focused on learning and assisting in RTL design tasksFull-time role, focused on testing and verifying RTL designs
Industry UsageUsed in semiconductor and chip design companies during early career stagesCommon in companies developing complex integrated circuits and chips

The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.

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Internship Asic Rtl Design Engineer jobs near you

Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)

SpaceX

Irvine, CA • On-site

$165K - $260K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted 23 days ago

SpaceX rating

8.7

Company rating: 8.7 out of 10

Based on 148 frontline employees who took The Breakroom Quiz

17th of 72 rated aerospace companies

Job description

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)
At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
RESPONSIBILITIES:
  • Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
  • Develop/improve physical design methodologies and automation scripts for various implementation steps
  • Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
  • Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
  • Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop

BASIC QUALIFICATIONS:
  • Bachelor's degree in electrical engineering, computer engineering or computer science
  • 5+ years of ASIC and/or physical design flow development experience in industry

PREFERRED SKILLS AND EXPERIENCE:
  • Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
  • Strong experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
  • Knowledge of deep sub-micron FinFET and CMOS solid state physics
  • Knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
  • Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
  • Familiar with CMOS analog circuit and physical design
  • Knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
  • Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
  • Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment

ADDITIONAL REQUIREMENTS:
  • Ability to work extended hours and weekends as needed to meet critical project milestones

COMPENSATION AND BENEFITS:
Pay range:
Physical Design Engineer/Senior: $165,000.00 - $260,000.00/per year
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.
Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.
ITAR REQUIREMENTS:
  • To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX's Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to EEOCompliance@spacex.com.

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About SpaceX

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Industry

Aerospace product and parts manufacturing, data services, guided missile and space vehicle manufacturing and satellite telecommunications

Company size

1,001 - 5,000 Employees

Headquarters location

Hawthorne, CA, US

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