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Internship Asic Rtl Design Engineer Jobs in Denver, CO

Protingent

FPGA Engineer

Englewood, CO · On-site

$130K - $165K/yr

FPGA Engineer Position Description : Protingent Staffing has an exciting direct hire FPGA Engineer ... Extensive knowledge with FPGA RTL design and development in System Verilog, Verilog, and/or VHDL

Broadcom

ASIC Design Verification Engineer

Broomfield, CO · On-site

$129K - $207K/yr

We are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a very dynamic market ...

Judge Group, Inc.

FPGA Firmware Engineer

Westminster, CO · On-site

$140K - $155K/yr

Our client is currently seeking an FPGA Firmware Engineer FPGA Firmware Engineer Location ... Design, implement, and verify FPGA logic (RTL) for EOIR and other payloads on AMD Versal adaptive ...

Stacy Witbeck

Internship: Signal Design

Littleton, CO · On-site

$25/hr

Starting at $25 Per Hour Description Support engineering tasks related to signal design for transit projects. This internship will be focused on developing computer automation tools to help with ...

Rocket Lab Corporation

Senior FPGA Engineer II

Littleton, CO

$104K - $143K/yr

... ASIC-based image processing algorithms. * Experience in both creating IP from scratch in RTL and ... PCB design and schematic capture and layout with tools such as Altium Designer. * Active TS/SCI ...

Rocket Lab Corporation

Senior FPGA Engineer II

Littleton, CO · On-site

$104K - $143K/yr

... ASIC-based image processing algorithms. * Experience in both creating IP from scratch in RTL and ... PCB design and schematic capture and layout with tools such as Altium Designer. * Active TS/SCI ...

Stacy Witbeck

Internship: Signal Design

Littleton, CO · On-site

$25/hr

Support engineering tasks related to signal design for transit projects. This internship will be focused on developing computer automation tools to help with various engineering tasks. Assignments ...

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All JobsAsic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer Jobs in Denver, CO

Internship Asic Rtl Design Engineer information

See Denver, CO salary details

$96.8K

$154.6K

$207.9K

How much do internship asic rtl design engineer jobs pay per year?

As of Aug 7, 2026, the average yearly pay for internship asic rtl design engineer in Denver, CO is $154,593.00, according to ZipRecruiter salary data. Most workers in this role earn between $135,400.00 and $185,300.00 per year, depending on experience, location, and employer.

What does an internship ASIC RTL design engineer do?

As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.

What are the key skills and qualifications needed to thrive as an internship ASIC RTL design engineer?

To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.

What is an internship ASIC RTL design engineer?

An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.

What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?

AspectInternship Asic Rtl Design EngineerAsic Verification Engineer
CredentialsTypically pursuing or recently completed a degree in Electrical Engineering or Computer EngineeringSimilar educational background, often with additional coursework in verification methodologies
Work EnvironmentInternship setting, supervised, focused on learning and assisting in RTL design tasksFull-time role, focused on testing and verifying RTL designs
Industry UsageUsed in semiconductor and chip design companies during early career stagesCommon in companies developing complex integrated circuits and chips

The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Denver, CO? The most popular types of Asic Rtl Design Engineer jobs in Denver, CO are:
What are popular job titles related to Internship Asic Rtl Design Engineer jobs in Denver, CO? For Internship Asic Rtl Design Engineer jobs in Denver, CO, the most frequently searched job titles are:
What job categories do people searching Internship Asic Rtl Design Engineer jobs in Denver, CO look for? The top searched job categories for Internship Asic Rtl Design Engineer jobs in Denver, CO are:
Internship Asic Rtl Design Engineer jobs near you
Infographic showing various Internship Asic Rtl Design Engineer job openings in Denver, CO as of August 2026, with employment types broken down into 72% Full Time, and 28% Contract. Highlights an 74% In-person, and 26% Remote job distribution, with an average salary of $154,593 per year, or $74.3 per hour.

FPGA Engineer

Protingent

Englewood, CO • On-site

$130K - $165K/yr

Full-time

Re-posted 21 days ago

Job description


Job Title: FPGA Engineer
Position Description: Protingent Staffing has an exciting direct hire FPGA Engineer with our client located in Englewood, CO.
Job Description:
  • We are looking for an experienced FPGA Engineer to lead the innovation of the next-generation space connectivity technology.

Job Responsibilities:
  • Design and manufacture systems including IC's and SoC type FPGA's
  • Design and implement high-speed communication processing subsystems.
  • Implement DSP, Security, and/or Networking algorithms on SoC type FPGAs.
  • Design for highly robust, distributed systems with emphasis on managing physical effects that originate from the harsh space environment.
  • Key contributor to Digital, Modem architecture and design.
  • Lead technical reviews with key stakeholders.
  • Work closely within a multi-disciplinary team to lead high-impact technical decisions about system design, implementation, and verification.

Job Qualifications:
  • 3+ year of experience in complex FPGA design
  • Experience in development of multiple FPGA designs through the full design life cycle from requirement through integration and delivery.
  • Extensive knowledge with FPGA RTL design and development in System Verilog, Verilog, and/or VHDL
  • Experience with Xilinx
  • Experience with development on SOC type FPGAs
  • Experience with signal processing functions and mixed-signal systems.
  • Hands on experience with FPGA's build flow including design, synthesis, place & route, timing constraints and timing closure.
  • Hands on with debug methodologies and lab debug experience.
  • B.Sc. in Electrical Engineering or equivalent with emphasis on signal processing.
  • Highly motivated, team player driven to solve problems and achieve high quality results.

Preferred Job Qualifications:
  • Experience with development of the Xilinx Versal SOC including Programmable Logic, AIE Cores, and ARM Core processors
  • Experience with design, verification and analysis design tools such as Vivado, Vitis, Synopsis, Questasim, linters and CDC
  • Experience Implementing DSP communication Algorithms, commercial Security Algorithms, and/or Networking Algorithms.
  • Experience implementing very High Speed SERDES protocols such as 10G/25G Ethernet, JESD204C, and Aurora
  • Experience with Channelizing, Beamforming and MIMO systems.
  • Experience with implementing memory storage systems.
  • Able to write scripts in MATLAB, python, TCL or other scripting languages.
  • Experience in space system development.
  • Space enthusiast.

Job Details:
  • Job Type: Direct Hire
  • Salary Range: $130K-$165K.
  • Location: Englewood, CO.
  • ITAR obligations are associated with this role, U.S. citizenship, U.S. legal permanent resident status, or protected person status under 8 U.S.C. § 1324b(a) (1), (3) is required.

About Protingent: Protingent is an Award-Winning provider of top-tier Engineering and IT talent, trusted by companies at the forefront of innovation - from Software and Aerospace to AI, Clean Tech, Medical Devices, and Connected Technologies. We're passionate about making a positive impact by connecting exceptional talent with meaningful opportunities and helping our clients build the future.
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