SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... RTL/design tradeoffs * Resolve design/timing/congestion and flow issues, identify potential ...
SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... RTL/design tradeoffs * Resolve design/timing/congestion and flow issues, identify potential ...
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Irvine, CA · On-site
$165K - $260K/yr
... SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... RTL/design tradeoffs * Resolve design/timing/congestion and flow issues, identify potential ...
Sr. SOC/ASIC Physical Design Engineer (Silicon Engineering)
Irvine, CA · On-site
$165K - $260K/yr
... SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... RTL/design tradeoffs * Resolve design/timing/congestion and flow issues, identify potential ...
Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Duration ... Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ...
Quick apply
Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Duration ... Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ...
Senior FPGA / RTL Design Engineer - Signal Processing
Irvine, CA · On-site
$125K - $195K/yr
THE OPPORTUNITY Silvus is seeking a Senior FPGA/RTL Design Engineer who will report to the Director ... Experience with communication systems on FPGA or ASIC designs. WORKING CONDITIONS & PHYSICAL ...
Senior FPGA / RTL Design Engineer - Signal Processing
Irvine, CA · On-site
$125K - $195K/yr
THE OPPORTUNITY Silvus is seeking a Senior FPGA/RTL Design Engineer who will report to the Director ... Experience with communication systems on FPGA or ASIC designs. WORKING CONDITIONS & PHYSICAL ...
Principal Digital Design Engineer
Irvine, CA · On-site
$190K - $225K/yr
Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project ... Familiarity with LLM-assisted RTL or HDL generation tools (e.g., Copilot for hardware, or general ...
Principal Digital Design Engineer
Irvine, CA · On-site
$190K - $225K/yr
Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project ... Familiarity with LLM-assisted RTL or HDL generation tools (e.g., Copilot for hardware, or general ...
Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project ... Familiarity with LLM-assisted RTL or HDL generation tools (e.g., Copilot for hardware, or general ...
Quick apply
Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project ... Familiarity with LLM-assisted RTL or HDL generation tools (e.g., Copilot for hardware, or general ...
Digital Design Engineer
$180K - $250K/yr
Strong fundamentals in digital ASIC design, micro-architecture, and best RTL coding methods. * Firmware / embedded C development, including bare-metal programming on an on-chip RISC CPU IP (e.g ...
Quick apply
Digital Design Engineer
$180K - $250K/yr
Strong fundamentals in digital ASIC design, micro-architecture, and best RTL coding methods. * Firmware / embedded C development, including bare-metal programming on an on-chip RISC CPU IP (e.g ...
Principal Digital Design Engineer
Irvine, CA · On-site
$146K/yr
Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project ... Familiarity with LLM-assisted RTL or HDL generation tools (e.g., Copilot for hardware, or general ...
Principal Digital Design Engineer
Irvine, CA · On-site
$146K/yr
Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project ... Familiarity with LLM-assisted RTL or HDL generation tools (e.g., Copilot for hardware, or general ...
DDR Design Engineer
Irvine, CA · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
DDR Design Engineer
Irvine, CA · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
Design Verification Engineer - Remote - Contract opportunity
Irvine, CA · Remote
$139K - $169K/yr
... seeking an ASIC Design Verification Engineer whose role will be to verify the functionality ... RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on ...
Quick apply
Design Verification Engineer - Remote - Contract opportunity
Irvine, CA · Remote
$139K - $169K/yr
... seeking an ASIC Design Verification Engineer whose role will be to verify the functionality ... RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on ...
DDR Design Engineer
Irvine, CA · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
DDR Design Engineer
Irvine, CA · On-site
As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...
SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... RTL design, chip bring-up, and post-silicon validation experience * Ability to work in a dynamic ...
SR. ASIC DESIGN VERIFICATION ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... RTL design, chip bring-up, and post-silicon validation experience * Ability to work in a dynamic ...
Debug SoC Design Engineer
$122K - $214K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...
Debug SoC Design Engineer
$122K - $214K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...
Debug SoC Design Engineer
$175K - $308K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...
Debug SoC Design Engineer
$175K - $308K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...
Debug SoC Design Engineer
$175K - $308K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...
Debug SoC Design Engineer
$175K - $308K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...
Debug SoC Design Engineer
$175K - $308K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...
Debug SoC Design Engineer
$175K - $308K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...
Debug SoC Design Engineer
$122K - $214K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...
Debug SoC Design Engineer
$122K - $214K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...
Debug SoC Design Engineer
$122K - $214K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...
Debug SoC Design Engineer
$122K - $214K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...
Senior FPGA / RTL Design Engineer - Signal Processing
$125K - $195K/yr
Fixed point design of signal processing blocks while working with systems engineers. * RTL coding ... Experience with communication systems on FPGA or ASIC designs. WORKING CONDITIONS AND PHYSICAL ...
Senior FPGA / RTL Design Engineer - Signal Processing
$125K - $195K/yr
Fixed point design of signal processing blocks while working with systems engineers. * RTL coding ... Experience with communication systems on FPGA or ASIC designs. WORKING CONDITIONS AND PHYSICAL ...
Debug SoC Design Engineer
$175K - $308K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...
Debug SoC Design Engineer
$175K - $308K/yr
... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...
Internship Asic Rtl Design Engineer information
See Corona, CA salary details
$97K - $107.1K
16% of jobs
$107.1K - $117.2K
3% of jobs
$117.2K - $127.4K
4% of jobs
$130.3K is the 25th percentile. Wages below this are outliers.
$127.4K - $137.5K
6% of jobs
The median wage is $143.9K / yr.
$137.5K - $147.6K
33% of jobs
$147.6K - $157.8K
3% of jobs
$157.8K - $167.9K
2% of jobs
$174.6K is the 75th percentile. Wages above this are outliers.
$167.9K - $178K
12% of jobs
$178K - $188.1K
5% of jobs
$188.1K - $198.3K
4% of jobs
$198.3K - $208.4K
12% of jobs
$97K
$155K
$208.4K
How much do internship asic rtl design engineer jobs pay per year?
What does an internship ASIC RTL design engineer do?
What are the key skills and qualifications needed to thrive as an internship ASIC RTL design engineer?
What is an internship ASIC RTL design engineer?
What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?
| Aspect | Internship Asic Rtl Design Engineer | Asic Verification Engineer |
|---|---|---|
| Credentials | Typically pursuing or recently completed a degree in Electrical Engineering or Computer Engineering | Similar educational background, often with additional coursework in verification methodologies |
| Work Environment | Internship setting, supervised, focused on learning and assisting in RTL design tasks | Full-time role, focused on testing and verifying RTL designs |
| Industry Usage | Used in semiconductor and chip design companies during early career stages | Common in companies developing complex integrated circuits and chips |
The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.
$165K - $260K/yr
Full-time
Medical, Dental, Vision, Life, Retirement, PTO
Re-posted 16 days ago
SpaceX rating
8.8
Based on 147 frontline employees who took The Breakroom Quiz
15th of 72 rated aerospace companies
Job description
SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING)
At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
RESPONSIBILITIES:
- Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)
- Develop/improve physical design methodologies and automation scripts for various implementation steps
- Closely collaborate with the ASIC design team to drive architectural feasibility studies, develop timing, power and area design targets, and explore RTL/design tradeoffs
- Resolve design/timing/congestion and flow issues, identify potential solutions and drive execution
- Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration and voltage drop
BASIC QUALIFICATIONS:
- Bachelor's degree in electrical engineering, computer engineering or computer science
- 5+ years of ASIC and/or physical design flow development experience in industry
PREFERRED SKILLS AND EXPERIENCE:
- Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
- Strong experience with industry standard EDA tools including understanding of their capabilities and underlying algorithms
- Knowledge of deep sub-micron FinFET and CMOS solid state physics
- Knowledge of CMOS digital design principles, basic standard cells their functionality, standard cell libraries
- Understanding of CMOS power dissipation in deep submicron processes leakage/dynamic
- Familiar with CMOS analog circuit and physical design
- Knowledge of DFT/Scan/MBIST/LBIST and understanding of their impact on physical design flows
- Good scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
- Self-driven individual with a can-do attitude, willing to learn, and an ability to work in a dynamic group environment
ADDITIONAL REQUIREMENTS:
- Ability to work extended hours and weekends as needed to meet critical project milestones
COMPENSATION AND BENEFITS:
Pay range:
Physical Design Engineer/Senior: $165,000.00 - $260,000.00/per year
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.
Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.
About SpaceX
Sourced by ZipRecruiter
Industry
Aerospace product and parts manufacturing, data services, guided missile and space vehicle manufacturing and satellite telecommunications
Company size
1,001 - 5,000 Employees
Headquarters location
Hawthorne, CA, US