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Internship Asic Rtl Design Engineer Jobs in Cerritos, CA

SpaceX

Sr. ASIC Design Engineer (Starshield)

Hawthorne, CA · On-site

$160K - $225K/yr

As an ASIC Design Engineer on the Starshield team, you will be working on advanced development ... Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level ...

Phizenix

Digital Design Engineer

Irvine, CA · On-site

$180K - $250K/yr

Strong fundamentals in digital ASIC design, micro-architecture, and best RTL coding methods. * Firmware / embedded C development, including bare-metal programming on an on-chip RISC CPU IP (e.g ...

Silvus Technologies

FPGA Design Engineer

Los Angeles, CA · On-site

$100K - $140K/yr

THE OPPORTUNITY Silvus is seeking a Senior FPGA / RTL Design Engineer reporting to the Director of ... Experience with communication systems on FPGA or ASIC designs. COMPENSATION The pay range is NOT a ...

Apple

DDR Design Engineer

Irvine, CA · On-site

As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...

Apple

DDR Design Engineer

Irvine, CA · On-site

As a logic design engineer, you will be involved in all phases of the design, from concept study ... You will provide high-quality RTL description, including assertions, for the design. Use formal ...

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All JobsAsic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer Jobs in Cerritos, CA

Internship Asic Rtl Design Engineer information

See Cerritos, CA salary details

$97.9K

$156.4K

$210.3K

How much do internship asic rtl design engineer jobs pay per year?

As of Aug 21, 2026, the average yearly pay for internship asic rtl design engineer in Cerritos, CA is $156,384.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,900.00 and $187,400.00 per year, depending on experience, location, and employer.

What is an internship ASIC RTL design engineer?

An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.

What does an internship ASIC RTL design engineer do?

As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.

What are the key skills and qualifications needed to thrive as an internship ASIC RTL design engineer?

To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.

What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?

AspectInternship Asic Rtl Design EngineerAsic Verification Engineer
CredentialsTypically pursuing or recently completed a degree in Electrical Engineering or Computer EngineeringSimilar educational background, often with additional coursework in verification methodologies
Work EnvironmentInternship setting, supervised, focused on learning and assisting in RTL design tasksFull-time role, focused on testing and verifying RTL designs
Industry UsageUsed in semiconductor and chip design companies during early career stagesCommon in companies developing complex integrated circuits and chips

The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.

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Internship Asic Rtl Design Engineer jobs near you
Infographic showing various Internship Asic Rtl Design Engineer job openings in Cerritos, CA as of June 2026, with employment types broken down into 1% Internship, 3% As Needed, 76% Full Time, 3% Part Time, and 17% Contract. Highlights an 96% Physical, 1% Hybrid, and 3% Remote job distribution, with an average salary of $156,384 per year, or $75.2 per hour.

Lead ASIC DFT Engineer - Remote (PST time zone) - Contract Opportunity

Zodiac Solutions

Irvine, CA • Remote

Contractor

Re-posted 28 days ago

Job description

Title - Lead ASIC DFT Engineer

Location – Remote (must be aligned with PST time zone)

Duration – Contract Opportunity

Required Visa: Any Visa

Job Description

Key skills for Lead ASIC DFT:

please see these key words of in the project description for the profile consideration.

  “SCAN, ATPG, MBIST, Timing Simulations,  SDF, SDC ,  PSV, Diagnosys ,  Pattern Retargeting , Pattern porting,  DRCs,  TetraMax, DFTMax “

Experience

10+ years of hands-on experience in ASIC Design-for-Test (DFT)

Role Summary

We are seeking a highly experienced Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for complex ASIC and SoC designs. This role requires deep technical ownership across DFT architecture, scan insertion, ATPG, MBIST/LBIST, JTAG, boundary scan, and post-silicon validation, along with the ability to lead cross-functional debug efforts and drive resolution of critical silicon issues.

The ideal candidate will have strong hands-on expertise in DFT fundamentals, fault models, test coverage, diagnosis, and debug, as well as the ability to evaluate and adopt emerging DFT methodologies and architecture schemes to improve robustness, quality, and yield.

Key Responsibilities

  • Lead DFT architecture, implementation, verification, and sign-off for complex ASIC and SoC designs.
  • Drive scan architecture, scan insertion, scan chain stitching, and scan compression workflows to achieve high coverage and robust testability.
  • Own MBIST/LBIST integration, implementation, verification, and debug across design and silicon bring-up phases.
  • Perform DFT debug, failure analysis, root-cause investigation, and fault coverage closure for complex silicon issues.
  • Develop and validate DFT constraints, including DFT SDC, timing checks, and DFT-specific timing analysis.
  • Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to resolve integration and implementation issues.
  • Support ATPG pattern generation, ATPG simulations, DRC analysis, test coverage analysis, and diagnosis/debug.
  • Work on JTAG, boundary scan, iJTAG, SSN, and IP-level DFT integration.
  • Review RTL, synthesis, LEC, and physical design impacts on DFT implementation and test quality.
  • Act as a technical escalation point for advanced DFT and post-silicon debug issues.
  • Mentor junior and mid-level DFT engineers and promote best practices in DFT methodology and automation.
  • Develop scripts and automation using TCL, PERL, or Python to improve flow efficiency and debug productivity.

Required Skills & Qualifications

  • Strong hands-on experience in ASIC DFT with end-to-end ownership.
  • Solid understanding of DFT fundamentals, fault models, test techniques, and test coverage concepts.
  • Deep expertise in scan architecture, ATPG, MBIST, LBIST, JTAG, boundary scan, and silicon debug.
  • Hands-on experience with Synopsys, Cadence, and Siemens/Mentor EDA tools.
  • Proven experience in scan insertion, ATPG setup, simulation, debug, and DRC analysis.
  • Experience with MBIST implementation and verification; SMS experience preferred.
  • Experience with scan architecture and scan chain stitching; Tessent/SSN experience preferred.
  • Strong understanding of PLLs, RTL design, synthesis flows, logical equivalence checking (LEC), and physical design implementation.
  • Proven post-silicon debug and silicon bring-up experience.
  • Exposure to large SoC designs, hierarchical DFT flows, and multi-domain integration challenges.
  • Strong communication skills and the ability to work independently with minimal ramp-up.

Preferred Experience

  • MBIST post-silicon validation.
  • ATPG simulations and fault coverage debug.
  • DFT RTL, DFD, DFT verification, and IP-level DFT integration.
  • DFT SDC creation and DFT timing closure support.
  • Boundary scan, iJTAG, SSN, and design-for-debug methodologies.
  • TCL/PERL scripting for DFT automation, reporting, and debug.
  • Experience working across multiple ASIC technology nodes and complex product development cycles.
  • Familiarity with yield learning, diagnosis, and manufacturing test optimization.