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Internship Asic Rtl Design Engineer Jobs in Austin, TX

SambaNova

Senior RTL Design Engineer

Austin, TX

S. in Electrical Engineering, Computer Engineering, or Computer Science * 5+ years of experience in ASIC RTL design * Solid foundation in computer architecture and digital logic design * Strong ...

SambaNova

Principal RTL Design Engineer

Austin, TX · On-site

B.S. in Electrical Engineering, Computer Engineering, or Computer Science * 7+ years of industry experience in ASIC RTL design * Mastery of synthesizable SystemVerilog for high-speed, high ...

SambaNova

Senior RTL Design Engineer

Austin, TX · On-site

$120K - $200K/yr

S. in Electrical Engineering, Computer Engineering, or Computer Science * 5+ years of experience in ASIC RTL design * Solid foundation in computer architecture and digital logic design * Strong ...

SambaNova

Principal RTL Design Engineer

Austin, TX · On-site

$180K - $255K/yr

B.S. in Electrical Engineering, Computer Engineering, or Computer Science * 7+ years of industry experience in ASIC RTL design * Mastery of synthesizable SystemVerilog for high-speed, high ...

Mythic

RTL Design Engineer

Austin, TX

$120K - $225K/yr

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.

Mythic

RTL Design Engineer

Austin, TX

$120K - $225K/yr

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.

Mythic

RTL Design Engineer

Austin, TX

$120K - $225K/yr

We're hiring experienced RTL Design Engineers from junior to senior levels to play a key role in designing and implementing the components that will bring our next-generation AI processors to life.

Apple

RTL Design Engineer

Austin, TX

$134K/yr

If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...

Apple

RTL Design Engineer

Austin, TX

$134K/yr

If you're passionate about taking on unsolved challenges, we have a great opportunity for a results-oriented and highly motivated RTL Design Engineer. This is an exciting position in the world class ...

Ericsson

ASIC Developer

Austin, TX · On-site

$117K - $175K/yr

Grow with us Senior RTL Design Engineer - Accelerator IP Location: Austin, TX (Hybrid; on-site ... End-to-end ASIC flow mastery: coding, linting, CDC, synthesis, timing closure. Proven ability to ...

Meta

ASIC Engineer, Design

Austin, TX

$146K/yr

ASIC Engineer, Design Responsibilities ... Develop micro-architecture, RTL coding, and design verification for complex IPs. * Work with ...

Mythic

Senior RTL Design Engineer

Austin, TX

$120K - $225K/yr

We're hiring experienced RTL Design Engineers to play a key role in designing and implementing the components that will bring our next-generation AI processors to life. About Us: Mythic is building ...

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All JobsAsic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer JobsInternship Asic Rtl Design Engineer Jobs in Austin, TX

Internship Asic Rtl Design Engineer information

See Austin, TX salary details

$93.2K

$148.9K

$200.2K

How much do internship asic rtl design engineer jobs pay per year?

As of Aug 31, 2026, the average yearly pay for internship asic rtl design engineer in Austin, TX is $148,875.00, according to ZipRecruiter salary data. Most workers in this role earn between $130,300.00 and $178,400.00 per year, depending on experience, location, and employer.

What is an internship ASIC RTL design engineer?

An Internship ASIC RTL (Register Transfer Level) Design Engineer is a student or recent graduate who assists in designing and developing digital integrated circuits (ICs) using hardware description languages like Verilog or VHDL. They work under the guidance of senior engineers to create, simulate, and verify RTL code for ASIC (Application Specific Integrated Circuit) projects. The role provides hands-on experience with the chip design process, including synthesis, timing analysis, and verification. Interns gain valuable exposure to industry-standard tools and methodologies, helping them prepare for a full-time engineering career.

What does an internship ASIC RTL design engineer do?

As an ASIC RTL Design Engineering intern, you'll typically work on tasks such as writing and verifying RTL code using languages like Verilog or VHDL, assisting with simulation and debugging, and collaborating closely with senior engineers on real design blocks. Interns often participate in design reviews, update documentation, and may get hands-on experience with synthesis and timing analysis tools. This role is highly collaborative and provides exposure to the complete ASIC development cycle, making it an excellent opportunity to build foundational skills and gain insight into industry-standard methodologies.

What are the key skills and qualifications needed to thrive as an internship ASIC RTL design engineer?

To thrive as an Internship ASIC RTL Design Engineer, you need a solid understanding of digital logic design, computer architecture, and proficiency in HDL languages like Verilog or VHDL, typically supported by coursework in electrical or computer engineering. Familiarity with industry-standard EDA tools such as Synopsys, Cadence, or Mentor Graphics, and simulation environments is highly valuable. Strong analytical thinking, attention to detail, and effective communication skills help interns collaborate with teams and learn quickly in a fast-paced environment. These skills and qualities are essential for contributing to complex chip design projects and ensuring accuracy and efficiency in RTL development.

What is the difference between Internship Asic Rtl Design Engineer vs Asic Verification Engineer?

AspectInternship Asic Rtl Design EngineerAsic Verification Engineer
CredentialsTypically pursuing or recently completed a degree in Electrical Engineering or Computer EngineeringSimilar educational background, often with additional coursework in verification methodologies
Work EnvironmentInternship setting, supervised, focused on learning and assisting in RTL design tasksFull-time role, focused on testing and verifying RTL designs
Industry UsageUsed in semiconductor and chip design companies during early career stagesCommon in companies developing complex integrated circuits and chips

The Internship Asic Rtl Design Engineer focuses on assisting in RTL design tasks during an internship, emphasizing learning and support. In contrast, the Asic Verification Engineer is responsible for verifying RTL designs to ensure functionality. Both roles require similar educational backgrounds but differ in responsibilities and work environment, with verification roles being more advanced and permanent.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Austin, TX?

The most popular types of Asic Rtl Design Engineer jobs in Austin, TX are:

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For Internship Asic Rtl Design Engineer jobs in Austin, TX, the most frequently searched job titles are:

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Internship Asic Rtl Design Engineer jobs near you
Infographic showing various Internship Asic Rtl Design Engineer job openings in Austin, TX as of August 2026, with employment types broken down into 53% Full Time, 10% Part Time, and 37% Contract. Highlights an 100% In-person job distribution, with an average salary of $148,875 per year, or $71.6 per hour.

Senior RTL Design Engineer

Austin, TX

SambaNova
See more jobs at SambaNovaexternal

Full-time

Posted 11 days ago

Job description

About the team About the role

The RTL design team builds the compute datapath, on-chip network, and memory subsystems inside SambaNova's RDU AI accelerator. Their work spans microarchitecture through tape-out: RTL implementation, PPA trade-offs, quality gates like lint, CDC, and LEC, and timing closure with 

About the role

SambaNova RTL Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs behind our AI acceleration systems. You'll own blocks within a larger subsystem, contributing sections of the microarchitecture specification, writing and debugging the RTL, and carrying your blocks through implementation, tape-out, and silicon bring-up. You'll work alongside principal engineers, architects, design verification, and physical design, and take on larger blocks as you build depth in our architecture

Required Qualifications
  • B.S. in Electrical Engineering, Computer Engineering, or Computer Science
  • 5+ years of experience in ASIC RTL design
  • Solid foundation in computer architecture and digital logic design
  • Strong SystemVerilog RTL design skills for high-speed, high-performance ASICs
  • Experience making design decisions that trade off power, performance, and area
  • Knowledge of industry-standard interconnects and protocols including AXI, PCIe, Ethernet, and HBM or DDR
  • Experience with digital logic synthesis tools and static timing analysis
  • Proficiency with industry-standard tools for linting, clock domain crossing, and logical equivalence checking
  • Experience implementing SystemVerilog Assertions to check design intent
  • Familiarity with tools and simulators for hardware performance analysis and tuning
  • Familiarity with Git for managing release cycles
  • Scripting skills in Python and Linux shell
Preferred Qualifications
  • M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science
  • Exposure to a full ASIC development cycle through tape-out and production silicon
  • Interest in or knowledge of AI workload acceleration techniques
  • Experience with low-power design techniques such as clock gating and DVFS at advanced process nodes
  • Exposure to emulation or FPGA prototyping platforms for pre-silicon validation

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