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Internship Analog Layout Design Engineer Jobs in Oregon

Nvidia

OR · Hybrid

Propose layout design trade-offs to the PTL for resolution and implementation. What we need to see: * Hold a B.S. Electrical Engineering or equivalent experience * Minimum of 5+ years proven ...

Posted today

Intel

Silicon Packaging Design Engineer

Hillsboro, OR

$148K/yr

Key Responsibilities: - Design and implement physical layout and routing of silicon interposers and ... experience with Analog/Mixed Signal fundamentals for signal integrity assessments and I/O ...

Apple

SerDes Circuit Design Engineer

Beaverton, OR

We are seeking talented Analog Mixed-Signal designers to join our high-speed SerDes team! Our team ... You will drive mask design to implement layout view of designs. You will closely work with SOC ...

Apple

SerDes Circuit Design Engineer

Beaverton, OR · On-site

We are seeking talented Analog Mixed-Signal designers to join our high-speed SerDes team. Our team ... including layout supervision, bench evaluation, correlation, and characterization Concepts of ...

Intel

Mixed Signal Logic Design Engineer

Hillsboro, OR · On-site

Develop behavioral models that represent analog and mixed-signal circuit blocks using SystemVerilog ... internship experiences. * BS degree in Electrical Engineering or Computer Engineering or similar ...

Intel

Memory Circuit Design Engineer

Hillsboro, OR

Memory bit-cell and complex periphery IC layout and automation. * Memory array/IP design, memory ... PhD with 1-2 years of professional experience gained through either internships or full-time ...

Apple

RTL Design Engineer

Beaverton, OR

$141K/yr

... Engineer. This is an exciting position in the world class Apple mixed-signal silicon design team ... analog circuit design and features. You will work with a variety of flows fundamental to modern ...

Apple

RTL Design Engineer

Beaverton, OR

$141K/yr

... Engineer. This is an exciting position in the world class Apple mixed-signal silicon design team ... analog circuit design and features. You will work with a variety of flows fundamental to modern ...

Apple

RTL Design Engineer

Beaverton, OR · On-site

... Engineer. This is an exciting position in the world class Apple mixed-signal silicon design team ... mixed-signal and analog circuit design and features. You will work with a variety of flows ...

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Internship Analog Layout Design Engineer information

What types of projects can an internship analog layout design engineer expect to work on, and how is mentorship typically provided in this role?

As an Internship Analog Layout Design Engineer, you will often work on projects involving the physical layout of analog and mixed-signal circuits, such as amplifiers, ADCs, or power management blocks. You can expect to collaborate closely with senior layout engineers and circuit designers, receiving guidance on best practices, design reviews, and tool usage. Mentorship is typically provided through regular check-ins, code reviews, and informal Q&A sessions, allowing you to learn industry-standard CAD tools and layout methodologies while contributing to real silicon tape-outs.

What are the key skills and qualifications needed to thrive as an internship analog layout design engineer?

To thrive as an Internship Analog Layout Design Engineer, you need a solid understanding of analog circuit fundamentals, semiconductor device physics, and coursework or experience in microelectronics. Familiarity with EDA tools such as Cadence Virtuoso, and exposure to industry standards like DRC/LVS checks, is typically required. Attention to detail, problem-solving ability, and effective communication are crucial soft skills for this role. These skills and qualifications are essential for creating reliable, efficient circuit layouts that meet technical specifications and support team collaboration in the design process.

What is the difference between Internship Analog Layout Design Engineer vs Analog Layout Design Engineer?

AspectInternship Analog Layout Design EngineerAnalog Layout Design Engineer
QualificationsEnrolled in or recent graduate of Electrical Engineering or related fieldBachelor's or Master's in Electrical Engineering or related field
Work EnvironmentInternship programs, entry-level projects, supervised tasksFull-time professional role, independent project work
ResponsibilitiesAssisting in layout design, learning tools, supporting senior engineersDesigning, optimizing, and verifying analog layouts independently

In summary, an Internship Analog Layout Design Engineer is a temporary, learning-focused role for students or recent graduates, while an Analog Layout Design Engineer is a full-time professional responsible for independent design tasks in the industry.

What does an internship analog layout design engineer do?

An Internship Analog Layout Design Engineer assists in the design and layout of analog integrated circuits under the guidance of experienced engineers. Their responsibilities include translating circuit schematics into physical layouts using specialized software, ensuring that the design meets performance and manufacturing requirements. Interns may also run design rule checks (DRC) and layout versus schematic (LVS) verifications to ensure correctness. This role helps interns build skills in analog design, CAD tools, and an understanding of semiconductor manufacturing processes.
Internship Analog Layout Design Engineer jobs near you

Analog and Mixed Signal Design Engineer

Intel Corporation

Hillsboro, OR • On-site

$164K - $269K/yr

Full-time

Medical, Retirement, PTO

Re-posted 27 days ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

19th of 156 rated electronics manufacturers

Job description

Job Details:
Job Description:
The Group: Intel's Advanced Design Foundational IP Organization (AD-FIP) within Design Technology Platform (DTP) focuses on pathfinding and development of advanced logic, memory, and analog/mixed-signal circuits to enable best-in-class Foundational IP collateral and product design across all generations of Intel process technology. Critical technologies AD-FIP delivers to Intel are Digital and Analog Standard Cell Libraries, Embedded Memory (SRAM, RF, ROM, eDRAM, Fuse, etc.), Analog Circuit Reference Designs (PLL, BGR, ADC, etc.), High-speed I/O Reference Designs (DDR, UCIe, PCIe, SerDes, GPIO), RF and Wireless Circuits (Wave Guide TX, Power Amplifier).
As an analog and mixed-signal IC designer your day-to-day responsibilities will include, but not always be limited to:
  • Developing, designing and testing circuit blocks including wireline IO AFEs, clocking circuits, and voltage regulator circuits as well as integrating them into Intel's leading technology test chips.
  • Capture of design and measurement results to guide the next generation of process technology and circuit specifications based on requirements for SoC building blocks and critical wireline interfaces.
  • Work closely with process and IP engineers to anticipate AMS IP requirements and use design and test results to inform and accelerate process technology and product development.

Qualifications:
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications:
  • Bachelor's degree in Electrical, Computer or Electrical and Computer Engineering, or related STEM field with 10+ years of experience, OR
  • Master's degree in Electrical, Computer or Electrical and Computer Engineering, or related STEM field with 8+ years of experience, OR
  • Ph.D. in Electrical, Computer or Electrical and Computer Engineering, or related STEM field with 3+ years of experience.

The qualifications listed below must meet the required years of experience associated with the candidate's degree level:
  • Experience with design of custom analog or mixed-signal circuits.
  • Analog or mixed signal design skills including specification, design or verification.

Preferred Qualifications:
Experience in one or more of the following areas is preferred:
  • GPIOs, high speed parallel or serial IO links and their subcomponents (data path, TX, RX, etc.), clock distribution, clock conditioning, clock recovery circuits, voltage regulators, voltage reference circuits, ADCs/DACs, inductors, transmission lines, RF and millimeter-wave circuits, test of custom analog and mixed-signal circuits.

Job Type:
Experienced Hire
Shift:
Shift 1 (United States of America)
Primary Location:
US, Oregon, Hillsboro
Additional Locations:
US, California, Santa Clara
Business group:
Intel Foundry strives to make every facet of semiconductor manufacturing state-of-the-art while delighting our customers -- from delivering cutting-edge silicon process and packaging technology leadership for the AI era, enabling our customers to design leadership products, global manufacturing scale and supply chain, through the continuous yield improvements to advanced packaging all the way to final test and assembly. We ensure our foundry customers' products receive our utmost focus in terms of service, technology enablement and capacity commitments. Employees in the Foundry Technology Manufacturing are part of a worldwide factory network that designs, develops, manufactures, and assembly/test packages the compute devices to improve the lives of every person on Earth.
Posting Statement:
All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.
Position of Trust
N/A
Benefits
We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.
Annual Salary Range for jobs which could be performed in the US: $164,470.00-269,100.00 USD
The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.
Work Model for this Role
This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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