Internship Analog Layout Design Engineer Jobs in Minnesota

Position Description: At ForwardEdge ASIC we specialize in best-in-class ASIC technology, 100% domestically traceable microelectronic solutions designed for performance in commercial, aerospace, defense, and security sectors. FEASIC operates a full-scale ASIC design shop with cross-disciplinary fluency between digital logic, analog/mixed-signal design, and physical layout, and sits at the intersection of advanced ASIC, FPGA, and microelectronics design. As a wholly owned subsidiary of Lockheed Martin, we combine the agility of a startup with the stability and scale of a Fortune 100 leader. We operate in a nimble, fast-paced environment of 80+ highly experienced and specialized engineers with over 25 years of ASIC/FPGA experience and more than 300 patents. We are looking for an entry-level Design Verification Engineer to join our growing verification team. This role is ideal for a recent graduate or early-career engineer who is interested in digital design verification, SystemVerilog, UVM, simulation, debugging, and advanced ASIC/SoC development.At ForwardEdge ASIC, you will work alongside experienced engineers, learn industry-standard verification methodologies, and contribute to the development of high-quality custom silicon solutions.Position SummaryAs a Design Verification Engineer, you will support the verification of ASIC, SoC, IP, subsystem, and FPGA designs. You will help develop testbenches, create tests, run simulations, debug failures, and contribute to coverage-driven verification under the guidance of senior engineers.This is a hands-on technical role with strong mentorship and learning opportunities. You will gain experience with modern verification methodologies, EDA tools, scripting, simulation debug, and the process of taking complex designs from specification through verification closure.Key Responsibilities• Support verification activities for ASIC, SoC, IP, subsystem, and FPGA designs.• Develop and maintain verification components using SystemVerilog and, where applicable, UVM.• Create and run directed and constrained-random tests to verify design functionality.• Assist in developing testbench components such as drivers, monitors, scoreboards, checkers, sequences, and coverage models.• Analyze design specifications and work with senior engineers to understand verification requirements.• Run simulations and regressions using industry-standard EDA tools.• Debug test failures using simulation logs, waveforms, assertions, and guidance from senior engineers.• Help collect and analyze functional coverage, code coverage, and regression results.• Document verification work, test results, debug findings, and issue resolutions.• Collaborate with design, verification, firmware, FPGA, and project teams to resolve issues.• Learn and apply best practices in verification methodology, automation, scripting, and reusable testbench development.• Participate in design reviews, verification reviews, and technical discussions.Qualifications• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related technical field.• Academic, internship, co-op, research, or project experience related to digital logic design, verification, computer architecture, embedded systems, or FPGA development.• Basic understanding of digital logic, RTL design concepts, and hardware description languages.• Exposure to SystemVerilog, Verilog, VHDL, or another hardware description/verification language.• Familiarity with simulation, debugging, test development, or verification concepts.• Basic scripting or programming experience using languages such as Python, Perl, Tcl, shell scripting, C, or C++.• Strong analytical and problem-solving skills.• Willingness to learn modern ASIC verification methodologies, including UVM, constrained-random verification, assertions, and coverage-driven verification.• Ability to read technical documentation, specifications, and design descriptions.• Good written and verbal communication skills.• Ability to work effectively in a collaborative engineering environment.Preferred Qualifications• Internship, co-op, academic, or project experience with ASIC, FPGA, SoC, or digital design verification.• Coursework or project experience with SystemVerilog, Verilog, digital design, computer architecture, embedded systems, or VLSI design.• Exposure to UVM or object-oriented programming concepts.• Experience writing testbenches for RTL modules.• Familiarity with waveform debugging tools and simulation flows.• Exposure to industry-standard EDA tools for simulation, debug, or coverage analysis.• Experience with FPGA development boards, embedded processors, or hardware/software integration.• Familiarity with protocols or interfaces such as AMBA, AXI, APB, AHB, PCIe, Ethernet, DDR, USB, MIPI, SPI, I2C, or UART.• Exposure to assertions, functional coverage, code coverage, or regression automation.• Experience using version control systems such as Git.• Interest in ASIC design services, custom silicon development, or customer-focused engineering environments.Why Join ForwardEdge ASIC?At ForwardEdge ASIC, you will have the opportunity to begin your career working on advanced ASIC and FPGA programs with an experienced engineering team. You will receive mentorship from senior verification engineers, gain hands-on exposure to industry-standard tools and methodologies, and contribute to high-quality custom silicon solutions for leading-edge applications.What We Offer• Work-Life Balance: Flexible 9/80 work schedule with every other Friday off• Competitive Comp & Benefits: Healthcare and medical coverage options, 401(k) retirement benefits with company contribution, generous holidays and PTO• Incentives: Eligibility for short-term and long-term incentive programsJoin ForwardEdge ASIC and be part of a team that thrives on innovation and excellence in ASIC design. Together, we build the technology that enables a safer, more resilient world. $115,000.00 - $135,000.00 Annually