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Internship Analog Layout Design Engineer Jobs in Idaho

Micron Technology

Layout Engineer, DEG

Boise, ID · On-site

$80 - $100/hr

Our layout engineering team drives the physical design foundations behind Micron ... Create partial custom layouts for selected device‑level or small analog blocks Minimum ...

Micron

Semiconductor Design Engineer

Boise, ID

Responsible for designing and analyzing digital and analog circuits used in the development of ... including layout verification and parasitic extractions of the circuits; 5. Performing ...

Micron

DRAM Design Engineer

Boise, ID

Job Summary As a Design Engineer at Micron Technology, Inc., you will be responsible for designing ... design, layout, and optimization across memory, logic, and analog domains * Assist with parasitic ...

Micron Technology

DRAM Design Engineer

Boise, ID · On-site

Job Summary As a Design Engineer at Micron Technology, Inc., you will be responsible for designing ... design, layout, and optimization across memory, logic, and analog domains * Assist with parasitic ...

3M HEALTHCARE

Semiconductor Design Engineer

Boise, ID · On-site

$125 - $150/hr

... design, layout, and optimization of memory, logic, and analog circuits. * Respond for parasitic ... Work with marketing, probe, assembly, test, process integration, and product engineering groups to ...

Micron Technology

Layout Engineer, DEG

Boise, ID · On-site

We work closely across global design, CAD, and verification groups, solving sophisticated ... Create partial custom layouts for selected device-level or small analog blocks Minimum ...

Micron Technology

Layout Engineer, DEG

Boise, ID

We work closely across global design, CAD, and verification groups, solving sophisticated ... Create partial custom layouts for selected device-level or small analog blocks Minimum ...

Micron Technology

Layout Engineer, DEG

Boise, ID

We work closely across global design, CAD, and verification groups, solving sophisticated ... Create partial custom layouts for selected device-level or small analog blocks Minimum ...

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Internship Analog Layout Design Engineer information

What does an internship analog layout design engineer do?

An Internship Analog Layout Design Engineer assists in the design and layout of analog integrated circuits under the guidance of experienced engineers. Their responsibilities include translating circuit schematics into physical layouts using specialized software, ensuring that the design meets performance and manufacturing requirements. Interns may also run design rule checks (DRC) and layout versus schematic (LVS) verifications to ensure correctness. This role helps interns build skills in analog design, CAD tools, and an understanding of semiconductor manufacturing processes.

What are the key skills and qualifications needed to thrive as an internship analog layout design engineer?

To thrive as an Internship Analog Layout Design Engineer, you need a solid understanding of analog circuit fundamentals, semiconductor device physics, and coursework or experience in microelectronics. Familiarity with EDA tools such as Cadence Virtuoso, and exposure to industry standards like DRC/LVS checks, is typically required. Attention to detail, problem-solving ability, and effective communication are crucial soft skills for this role. These skills and qualifications are essential for creating reliable, efficient circuit layouts that meet technical specifications and support team collaboration in the design process.

What types of projects can an internship analog layout design engineer expect to work on, and how is mentorship typically provided in this role?

As an Internship Analog Layout Design Engineer, you will often work on projects involving the physical layout of analog and mixed-signal circuits, such as amplifiers, ADCs, or power management blocks. You can expect to collaborate closely with senior layout engineers and circuit designers, receiving guidance on best practices, design reviews, and tool usage. Mentorship is typically provided through regular check-ins, code reviews, and informal Q&A sessions, allowing you to learn industry-standard CAD tools and layout methodologies while contributing to real silicon tape-outs.

What is the difference between Internship Analog Layout Design Engineer vs Analog Layout Design Engineer?

AspectInternship Analog Layout Design EngineerAnalog Layout Design Engineer
QualificationsEnrolled in or recent graduate of Electrical Engineering or related fieldBachelor's or Master's in Electrical Engineering or related field
Work EnvironmentInternship programs, entry-level projects, supervised tasksFull-time professional role, independent project work
ResponsibilitiesAssisting in layout design, learning tools, supporting senior engineersDesigning, optimizing, and verifying analog layouts independently

In summary, an Internship Analog Layout Design Engineer is a temporary, learning-focused role for students or recent graduates, while an Analog Layout Design Engineer is a full-time professional responsible for independent design tasks in the industry.

What cities in Idaho are hiring for Internship Analog Layout Design Engineer jobs?

Cities in Idaho with the most Internship Analog Layout Design Engineer job openings:

Internship Analog Layout Design Engineer jobs near you

Principal Analog Design Engineer - Mixed-Signal PHY (Clocking / High-Speed I/O)

Micron Technology

Boise, ID • On-site

Full-time

Medical, Dental, Vision, PTO

Posted 26 days ago

Micron Technology rating

8.6

Company rating: 8.6 out of 10

Based on 43 frontline employees who took The Breakroom Quiz

26th of 161 rated electronics manufacturers

Job description

Our vision is to transform how the world uses information to enrich life for all.
Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.
Micron's Interface Pathfinding team builds and validates innovative PHY solutions for high-speed chip-to-chip and memory interconnect. Our focus is on pushing the boundaries of what is possible in high-speed signaling and validating those boundaries with real hardware data.
As a Principal Analog Design Engineer, you will be at the forefront of developing custom and original analog circuits. This is not integration or maintenance work, but an ambitious opportunity to contribute to world-class clocking, transmitter, and receiver circuits. You will own the complete lifecycle of building, from specifications through to post-silicon characterization.
Responsibilities:
  • Lead the development of specialized analog components, focusing primarily on clocking (PLL, DLL, CDR) and transmitter/receiver circuits.
  • Contribute to the top-level PHY analog architecture decisions, including clocking topology and signal chain partitioning.
  • Build and maintain transistor-level simulation testbenches; perform process corner, statistical sampling, and evaluate variations to characterize build margin and yield sensitivity.
  • Define and detail clear interface specifications between custom analog blocks and the digital control wrapper.
  • Collaborate closely with the layout team to guide custom analog layout and support post-silicon characterization in the lab.
Minimum Qualifications:
  • BS, MS, or PhD in Electrical Engineering or related field, or equivalent experience.
  • 10+ years of analog/mixed-signal IC build experience with at least one tape-out in a primary circuit ownership role.
  • Deep expertise in clocking circuit building - PLL, DLL, or CDR architecture and transistor-level implementation in sophisticated CMOS nodes.
  • Strong transistor-level simulation skills using HSpice or equivalent; comfort with corner, Monte Carlo, and mismatch analysis for yield-aware development.
  • Proven understanding of jitter analysis and its impact on high-speed link timing margins.
  • Ability to use AI/ML/LLMs for productivity and efficiency
Preferred Qualifications:
  • Experience with high-speed transmitter development - output driver architectures, pre-emphasis, swing control, and impedance matching for multi-Gbps die-to-die or SerDes interfaces.
  • Background in rapid receiver development - sense amplifiers, CTLE/DFE equalization, sampler development, and threshold calibration.
  • Familiarity with die-to-die or chip-to-chip PHY architectures - UCIe, AIB, BoW, or proprietary short-reach interconnect standards.
  • Experience working with OTP/fuse-based calibration architectures and analog trim loop implementation.
  • Post-silicon characterization experience - correlating simulation results to measured eye diagrams, BER curves, phase noise plots, and jitter histograms on real hardware.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on micron.com/careers/benefits.
Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, citizenship status, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.
To learn about your right to work click here.
To learn more about Micron, please visit micron.com/careers
For US Sites Only: To request assistance with the application process and/or for reasonable accommodations, please contact Micron's People Organization at hrsupport_na@micron.com or 1-800-336-8918 (select option #3)
Micron Prohibits the use of child labor and complies with all applicable laws, rules, regulations, and other international and industry labor standards.
Micron does not charge candidates any recruitment fees or unlawfully collect any other payment from candidates as consideration for their employment with Micron.
AI alert: Candidates are encouraged to use AI tools to enhance their resume and/or application materials. However, all information provided must be accurate and reflect the candidate's true skills and experiences. Misuse of AI to fabricate or misrepresent qualifications will result in immediate disqualification.
Fraud alert: Micron advises job seekers to be cautious of unsolicited job offers and to verify the authenticity of any communication claiming to be from Micron by checking the official Micron careers website in the About Micron Technology, Inc.

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