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Intern Asic Design Engineer Jobs in Riverside, CA

Broadcom, Inc.

ASIC Design Verification Engineer

Irvine, CA · On-site

$129K - $207K/yr

We are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a very dynamic market ...

Apple

Debug SoC Design Engineer

Irvine, CA

$122K - $214K/yr

... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Apple

Debug SoC Design Engineer

Irvine, CA

$122K - $214K/yr

... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Apple

Debug SoC Design Engineer

Irvine, CA

$122K - $214K/yr

... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Apple

Debug SoC Design Engineer

Irvine, CA

$175K - $308K/yr

... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Apple

Debug SoC Design Engineer

Irvine, CA

$175K - $308K/yr

... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Apple

Debug SoC Design Engineer

Irvine, CA

$175K - $308K/yr

... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Apple

Debug SoC Design Engineer

Irvine, CA

$175K - $308K/yr

... integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC ... This is a highly visible role, where you will be at the center of the ASIC debug efforts ...

Silvus Technologies

FPGA Design Engineer

Irvine, CA

$132K - $181K/yr

FPGA Design Engineers are responsible for the efficient implementation of novel signal processing ... Experience with communication systems on FPGA or ASIC designs. WORKING CONDITIONS AND PHYSICAL ...

Marvell

Digital Design Engineer

Irvine, CA

$146K/yr

Responsible for design, verification, implementation (ASIC) for high-performance, physical layer ... Develop ASIC specification, architecture, and micro-architecture of major functional blocks in ...

Marvell Technology, Inc.

Digital Design Engineer

Irvine, CA · On-site

$146K/yr

Responsible for design, verification, implementation (ASIC) for high-performance, physical layer ... Develop ASIC specification, architecture, and micro-architecture of major functional blocks in ...

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Showing results 1-20

All JobsIntern Asic Design Engineer JobsIntern Asic Design Engineer Jobs in Riverside, CA

Intern Asic Design Engineer information

See Riverside, CA salary details

$9

$20

$38

How much do intern asic design engineer jobs pay per hour?

As of Jul 19, 2026, the average hourly pay for intern asic design engineer in Riverside, CA is $20.22, according to ZipRecruiter salary data. Most workers in this role earn between $15.05 and $22.55 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an Intern ASIC Design Engineer, and why are they important?

To thrive as an Intern ASIC Design Engineer, you need a solid background in digital logic design, computer architecture, and a relevant degree in electrical or computer engineering. Familiarity with hardware description languages such as Verilog or VHDL, simulation tools, and EDA software is typically required. Strong analytical thinking, attention to detail, teamwork, and effective communication make an intern stand out in this role. These skills and qualities are crucial for designing reliable, high-performance integrated circuits and collaborating efficiently within engineering teams.

What does an Intern ASIC Design Engineer do?

An Intern ASIC Design Engineer assists in designing, developing, and verifying Application-Specific Integrated Circuits (ASICs) under the guidance of senior engineers. Their responsibilities often include working with hardware description languages like Verilog or VHDL, running simulations, debugging designs, and performing tests to ensure functionality and performance. Interns may also help with documentation, design reviews, and collaborating with cross-functional teams. This role provides hands-on experience in the semiconductor industry and helps build foundational skills for a career in hardware engineering.

What is the difference between Intern Asic Design Engineer vs Intern Digital Design Engineer?

AspectIntern Asic Design EngineerIntern Digital Design Engineer
CredentialsTypically pursuing or holding a degree in Electrical Engineering or Computer EngineeringTypically pursuing or holding a degree in Electrical Engineering or Computer Engineering
Work EnvironmentDesign teams focused on ASIC development, hardware design labs, collaborative projectsDigital circuit design, simulation, verification, and hardware testing environments
Industry UsageUsed in semiconductor companies, integrated circuit design firms, and hardware startupsCommon in semiconductor, electronics, and hardware development companies

Both roles involve working on digital hardware design, often requiring similar educational backgrounds. The main difference lies in the focus: Intern Asic Design Engineers work on the overall ASIC development process, while Intern Digital Design Engineers focus specifically on digital circuit design and verification. Both positions are essential in hardware development and often overlap in skills and work environment.

What types of projects and responsibilities can I expect as an Intern ASIC Design Engineer?

As an Intern ASIC Design Engineer, you can expect to work on a variety of tasks that support the design and verification of integrated circuits. Typical responsibilities include assisting with RTL coding, running simulations, analyzing test results, and documenting design processes. You'll often collaborate closely with senior engineers and cross-functional teams, gaining exposure to state-of-the-art tools and methodologies. This role provides a valuable learning environment where you're encouraged to ask questions, contribute to team discussions, and develop practical skills that are highly valued in the semiconductor industry.
What are popular job titles related to Intern Asic Design Engineer jobs in Riverside, CA? For Intern Asic Design Engineer jobs in Riverside, CA, the most frequently searched job titles are:
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Intern Asic Design Engineer jobs near you
Infographic showing various Intern Asic Design Engineer job openings in Riverside, CA as of July 2026, with employment types broken down into 33% Internship, 34% Full Time, and 33% Part Time. Highlights an 100% In-person job distribution, with an average salary of $42,048 per year, or $20.2 per hour.
Senior Principal Digital Design Engineer

Senior Principal Digital Design Engineer

MaxLinear, Inc.

Irvine, CA • On-site

$186K - $228K/yr

Full-time

Medical, Retirement, PTO

Posted 21 days ago

Job description

Responsibilities
MaxLinear is seeking a Senior Principal Digital Design Engineer to join our team. In this role, you will focus on the following:
  • Define microarchitecture for complex subsystems (e.g., 200/400G 802.3, PCIe 6/7, DSP, FEC, data compression, AI/HW accelerators)
  • Analyze standards (PCI-SIG, IEEE 802.3, UALink, etc) and translate into implementable RTL
  • Work with cross-functional project teams (DV, PD, System/Firmware) to define product specifications (PPA), system architecture, HW/SW partitioning, and execution plan
  • Lead improvements to design methodology to maximize efficiency and predictability
  • RTL implementation in SystemVerilog of communication/DSP/packet-processing functions
  • Block-level verification including creation of Verilog or UVM testbenches
  • System-level verification in UVM+SysC environments including test case creation/debug, functional coverage specification, and code coverage analysis
  • Perform preliminary synthesis and power estimation, including SDC constraint specification and vector-driven power analysis
  • Perform design quality checks including lint, CDC and DFT-readiness checks
  • Support emulator-based verification including debug of SW driven test cases
  • Post silicon bring-up support and debug in lab; support system integration and production testing
  • Provide technical leadership in the ASIC design team to develop and productize next generation communication and data center SoCs

Qualifications
  • Expert in digital design including micro-architecture definition and area/power/timing optimization
  • Solid understanding of high-speed interfaces (Ethernet/PCIe), particularly MAC/PCS (or Transaction/Data Link/PHY logical) layers, and associated clocking, reset, and CDC considerations
  • Experience with performance modeling and analysis, including performance constraint identification and optimization
  • Extensive experience with ASIC front-end design flow including RTL coding (SystemVerilog), directed/randomized verification, simulation/emulation debug, lint/CDC checks, synthesis, power analysis and timing closure support
  • Knowledge of communications/DSP/FEC algorithms and experience with power/area efficient fixed-point ASIC implementation a plus
  • Familiar with SoC integration, including clock/reset architecture, bus protocols, embedded CPUs
  • Strong logical and creative problem-solving skills with excellent analytical and debugging skills
  • Solid written and verbal communication skills
  • Flexibility to ramp quickly on new technologies, products, and methodologies
  • Self-motivated with ability to provide leadership and work effectively in fast-paced environment
  • BS in Electrical Engineering or related + 11 years of experience, or MS + 9 years of experience, or Ph.D. + 6 years of experience

Compensation and Benefits
MaxLinear has a Total Compensation philosophy which includes base salary and annual discretionary bonus eligibility and many positions also include stock-based compensation.
MaxLinear's good faith estimate starting base salary range is: $186,000 to $228,000 Annually
We offer competitive benefits designed to support employee health, welfare, and retirement and some highlights are: health care benefits, 401k savings plan, Employee Stock Purchase Plan (ESPP), and paid time off.
The actual starting base salary will be determined by the match to certain role-related criteria such as educational degree(s) or equivalent, relevant work experience, skillset needed for the role, and geographic location; this is not an all-inclusive list as some roles may require unique skills or experience.
Qualified applicants will receive consideration for employment without regard to, and will not be discriminated against based on race, sex, religion, national origin, sexual orientation, gender identity, disability, or protected veteran status.
Company Overview
MaxLinear is a global, NASDAQ-traded company (MXL) where the entrepreneurial spirit is alive and well. We are a fabless system-on-chip product company, striving to improve the world's communication networks for everyone through our highly integrated radio-frequency (RF), analog, digital, and mixed-signal semiconductor solutions for access and connectivity, wired and wireless infrastructure, and industrial and multi-market applications.
We hire the best people in the industry and engage them in some of the most exciting opportunities that connect the world we live in today. Our growth has come from innovative, bold approaches to solving some of the world's most challenging communication technology problems in the most efficient and effective manner.
MaxLinear began by developing the world's first high-performance TV tuner chip using standard CMOS process technology. Others said we couldn't achieve the extremely high-performance requirements using CMOS, but we proved them wrong and achieved enduring global market leadership with our designs. Since then, we've developed a full line of products that drive 4G and 5G infrastructure; enable data center, metro and long-haul optical interconnects; bring 10Gbit to the home; power the IoT revolution; and enable robust and reliable communication in harsh industrial environments. Over the years, we've expanded through organic growth and through several acquisitions that have perfectly complemented our existing portfolio and enabled us to deliver complete end-to-end solutions in our target markets. One such example was the acquisition of Intel's Home Gateway Platform Division that added Wi-Fi, Ethernet, and Broadband Gateway Processor SoC technology to our connected home portfolio creating a complete and scalable platform of connectivity and access solutions to fully address our customers' needs.
Our headquarters are in Carlsbad, near San Diego, California. We also have major design centers in Irvine and San Jose, California; Valencia, Spain; Bangalore, India; Munich, Germany; Israel; and Singapore.
We have approximately 1,200 employees, a substantial majority of whom have engineering degrees and include masters and Ph.D. graduates from many of the premiere universities around the world. Our employees thrive on innovation, outstanding execution, outside-the-box thinking, nimbleness, and collaboration. Together, we form a high-energy business team that is focused on building the best and most innovative products on the market.

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