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Intern Asic Design Engineer Jobs in Riverside, CA

GreenWave Radios

Principal ASIC Design Engineer

Irvine, CA · On-site

$190K - $225K/yr

Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project scheduling, and technical mentoring/oversight * Own solution architecture end-to-end-taking marketing ...

Broadcom

ASIC Design Engineer

Irvine, CA

$108K - $172K/yr

We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power ...

Broadcom Inc.

ASIC Design Engineer

Irvine, CA · On-site

$127.10 - $203.40/hr

We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power ...

Broadcom, Inc.

ASIC Design Engineer

Irvine, CA · On-site

$108K - $172K/yr

We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power ...

Broadcom

ASIC Design Engineer

Irvine, CA

$127K - $203K/yr

We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power ...

Broadcom, Inc.

ASIC Design Engineer

Irvine, CA · On-site

$127K - $203K/yr

We are looking for an ASIC Implementation Engineer with demonstrated expertise in multiple disciplines including synthesis, design for test, floorplanning, place and route, clock methodology, power ...

Phizenix

Digital Design Engineer

Irvine, CA · On-site

$180K - $250K/yr

: Role Overview We are seeking an ASIC Design Engineer to own digital design, integration, and bring-up for production-grade high-speed interconnect silicon. You will translate micro-architecture into ...

OMNIVISION

Sr. Digital Design Engineer

Irvine, CA · On-site

We are looking for Digital Design Engineer for design and development of next generation image ... In depth hands-on experience in ASIC design flow: RTL coding, simulation, synthesis, static timing ...

OMNIVISION

Sr. Digital Design Engineer

Irvine, CA · On-site

$120K - $150K/yr

Description We are looking for Digital Design Engineer for design and development of next ... In depth hands-on experience in ASIC design flow: RTL coding, simulation, synthesis, static timing ...

OMNIVISION

Sr. Digital Design Engineer

Irvine, CA · On-site

$120K - $150K/yr

We are looking for Digital Design Engineer for design and development of next generation image ... In depth hands-on experience in ASIC design flow: RTL coding, simulation, synthesis, static timing ...

Purple Hires Inc

ASIC DFT Engineer

Irvine, CA · On-site

... Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for ... Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ...

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All JobsIntern Asic Design Engineer JobsIntern Asic Design Engineer Jobs in Riverside, CA

Intern Asic Design Engineer information

See Riverside, CA salary details

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$20

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How much do intern asic design engineer jobs pay per hour?

As of Aug 10, 2026, the average hourly pay for intern asic design engineer in Riverside, CA is $20.22, according to ZipRecruiter salary data. Most workers in this role earn between $15.05 and $22.55 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as an Intern ASIC Design Engineer, and why are they important?

To thrive as an Intern ASIC Design Engineer, you need a solid background in digital logic design, computer architecture, and a relevant degree in electrical or computer engineering. Familiarity with hardware description languages such as Verilog or VHDL, simulation tools, and EDA software is typically required. Strong analytical thinking, attention to detail, teamwork, and effective communication make an intern stand out in this role. These skills and qualities are crucial for designing reliable, high-performance integrated circuits and collaborating efficiently within engineering teams.

What does an Intern ASIC Design Engineer do?

An Intern ASIC Design Engineer assists in designing, developing, and verifying Application-Specific Integrated Circuits (ASICs) under the guidance of senior engineers. Their responsibilities often include working with hardware description languages like Verilog or VHDL, running simulations, debugging designs, and performing tests to ensure functionality and performance. Interns may also help with documentation, design reviews, and collaborating with cross-functional teams. This role provides hands-on experience in the semiconductor industry and helps build foundational skills for a career in hardware engineering.

What is the difference between Intern Asic Design Engineer vs Intern Digital Design Engineer?

AspectIntern Asic Design EngineerIntern Digital Design Engineer
CredentialsTypically pursuing or holding a degree in Electrical Engineering or Computer EngineeringTypically pursuing or holding a degree in Electrical Engineering or Computer Engineering
Work EnvironmentDesign teams focused on ASIC development, hardware design labs, collaborative projectsDigital circuit design, simulation, verification, and hardware testing environments
Industry UsageUsed in semiconductor companies, integrated circuit design firms, and hardware startupsCommon in semiconductor, electronics, and hardware development companies

Both roles involve working on digital hardware design, often requiring similar educational backgrounds. The main difference lies in the focus: Intern Asic Design Engineers work on the overall ASIC development process, while Intern Digital Design Engineers focus specifically on digital circuit design and verification. Both positions are essential in hardware development and often overlap in skills and work environment.

What types of projects and responsibilities can I expect as an Intern ASIC Design Engineer?

As an Intern ASIC Design Engineer, you can expect to work on a variety of tasks that support the design and verification of integrated circuits. Typical responsibilities include assisting with RTL coding, running simulations, analyzing test results, and documenting design processes. You'll often collaborate closely with senior engineers and cross-functional teams, gaining exposure to state-of-the-art tools and methodologies. This role provides a valuable learning environment where you're encouraged to ask questions, contribute to team discussions, and develop practical skills that are highly valued in the semiconductor industry.
What cities near Riverside, CA are hiring for Intern Asic Design Engineer jobs? Cities near Riverside, CA with the most Intern Asic Design Engineer job openings:
Intern Asic Design Engineer jobs near you
Infographic showing various Intern Asic Design Engineer job openings in Riverside, CA as of August 2026, with employment types broken down into 33% Internship, 34% Full Time, and 33% Part Time. Highlights an 100% In-person job distribution, with an average salary of $42,048 per year, or $20.2 per hour.

Principal ASIC Design Engineer

GreenWave Radios™

Irvine, CA • On-site

Full-time

Posted 25 days ago

Job description

InnoPhase Inc., DBA GreenWave Radios™, is at the forefront of innovation in Open RAN digital radios. Our cutting-edge solutions, powered by the Hermes64 RF SoC, are designed to enhance network energy efficiency while dramatically reducing operational expenses, with purpose-built silicon that is the heart of ORAN-based active antenna arrays.

Headquartered in San Diego, California, GreenWave Radios™ has established itself as a pioneer in delivering power-efficient digital-to-RF solutions. The company is supported by a talented team of over 100 engineers spread across four global R&D facilities. With an extensive portfolio of more than 120 global patents, GreenWave Radios™ continues to push the boundaries of radio technology and innovation.

To learn more about GreenWave Radios™ and hear what our employees have to say, visit the GreenWave™ certification profile at GreatPlacetoWork.com or explore our Home - GreenWave Radios website.

About the Role

We're looking for an experienced Principal Engineer/Manager to lead a small, high-impact team building next-generation cellular infrastructure radio Front Haul Gateway (FHGW) solutions in both FPGA and ASIC. You'll own everything from architecture through production—defining features, authoring device specifications, and driving the design flow for high-performance programmable logic with embedded Linux-based wireless communications software. This is a senior technical leadership and management role with direct influence on our market-leading cellular infrastructure products, working hands-on alongside experts across design, verification, firmware, and system engineering.

What You'll Do
  • Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project scheduling, and technical mentoring/oversight
  • Own solution architecture end-to-end—taking marketing requirements and translating to product specifications through production-quality programmable logic design, verification and hardware validation
  • Drive architecture / micro-architecture definition, CPU/bus/memory subsystem design, IP integration, and physical implementation for complex SoC designs
  • Collaborate with system engineering on Radio product specifications, ensuring alignment across the company
  • Partner with IP, design verification, firmware, software, and production teams to close design issues and meet program milestones
  • Refine development methodologies and enforce design quality standards across the team, including simulation, linting, clock-domain crossing checks, and formal verification
  • Collaborate with embedded Linux-based wireless communications software team that complements the FPGA/ASIC logic layer
What You Bring
  • 20+ years of experience in FPGA and SoC development and mass production, including a proven track record in a technical leadership and management role
  • MS or PhD in Electrical Engineering or equivalent
  • Deep expertise in Verilog and SystemVerilog, and front-end tooling (simulation, linting, CDC, formal verification)
  • Hands-on experience with packet processing designs including buffering, routing, transposing, combining, framing/de-framing packet based formats (e.g. Ethernet, O-RAN/eCPRI, etc)
  • Hands-on experience with AMBA AXI/AHB/APB bus protocol specification and implementation
  • Proven ability to define constraints, run synthesis and static timing analysis, and own a complete front-to-back AMD (Xilinx Vivado) FPGA implementation flow
  • Working knowledge of DFT/DFM, SCAN ATPG, BIST, and fault coverage analysis
  • Proficiency in SystemVerilog and other advanced design verification methodologies
  • Comfort with scripting and programming languages including C/C++, Perl, Tcl, and Python
  • Strong communication and presentation skills; ability to drive results under aggressive schedules across cross-functional teams
Nice to Have
  • Experience developing cellular infrastructure radio products, particularly 10/25Gbps Ethernet eCPRI connectivity to the DU and interface to RF ASICs.
  • Familiarity with O-RAN FS7.2x specifications or eCPRI/CPRI front haul protocols
  • Understanding of Array based radios including AAU and mMIMO
  • Exposure to AI-assisted EDA tools for synthesis, timing analysis, or verification (e.g., AI-driven placement/routing assistants, ML-based timing closure prediction, AI-guided power analysis)
  • Experience using Claude Code or similar AI coding assistants to accelerate design scripting, documentation, or code review — familiarity with agentic AI tools for engineering workflows is a genuine differentiator
  • Familiarity with LLM-assisted RTL or HDL generation tools (e.g., Copilot for hardware, or general-purpose LLMs prompted for Verilog/SystemVerilog generation and review)
  • Comfort using AI tools for verification productivity — assertion generation, coverage analysis, or ML-based bug prediction to speed up simulation closure
  • Experience applying AI to technical documentation workflows — LLM-assisted datasheet parsing, specification drafting, or design review summarization
  • General comfort adopting AI-augmented workflows to boost design productivity
Compensation and Benefits

At InnoPhase, dba GreenWave Radios, our total rewards package includes both a competitive base salary and pre-IPO stock options. The anticipated base salary range for this position is $190,000 to $225,000 annually. Actual compensation will be determined based on several factors, including market conditions, interview performance, skills, qualifications, experience, education, and geographic location. In addition to base pay, employees are eligible for a comprehensive benefits package. For detailed information on our benefits programs, please visit our website.