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Intern Asic Design Engineer Jobs in Riverside, CA

Purple Hires Inc

ASIC DFT Engineer

Irvine, CA · On-site

... Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for ... Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ...

Xcelerium

Senior VLSI Physical Design Engineer

Irvine, CA · On-site

$130 - $180/hr

About the Job We are seeking a highly skilled Senior SoC/ASIC Physical Design Engineer to lead and drive the physical design activities to successful closure by collaborating closely with RTL and ...

New

Broadcom Inc.

ASIC Verification Engineer

Irvine, CA · On-site

$101 - $162/hr

Logic design, Electronic circuit design and related course work to provide a broad background in the area of ASIC design and verification. * Proficiency with HDL language such as Verilog ...

Phizenix

Digital Design Lead

Irvine, CA

$180K - $200K/yr

... engineers and coordinate with verification, DFT, and physical design teams to meet project schedules. Required Skills & Experience * Proven track record as an RTL Design Lead on complex digital ASIC ...

Broadcom

ASIC Verification Engineer

Irvine, CA · On-site +1

ASIC Verification EngineerHigh Speed Interconnect Product (HSIP) Group TheOpportunity Broadcom is ... We design the industry's lowest-power, highest-performance PHYs that enable the world's fastest ...

Broadcom, Inc.

ASIC Verification Engineer

Irvine, CA · On-site

... design specification. • Develop advanced verification environment and testbench components in ... Job Requirements: • Bachelors in Engineering and 5+ years of related experience, or recent grad ...

Broadcom

ASIC Verification Engineer

Irvine, CA

Logic design, Electronic circuit design and related courseworkto provide a broad background in the area of ASIC design and verification. Proficiency with HDL language such as Verilog, SystemVerilog ...

Broadcom, Inc.

ASIC Verification Engineer

Irvine, CA · On-site

ASIC Verification Engineer High Speed Interconnect Product (HSIP) Group The Opportunity Broadcom is ... We design the industry's lowest-power, highest-performance PHYs that enable the world's fastest ...

Broadcom

ASIC Design Verification Engineer

Irvine, CA

$129K - $207K/yr

We are looking for highly skilled and efficient Constrained Random Design Verification engineers that want to verify new designs that can evolve rapidly at every generation in a very dynamic market ...

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Showing results 21-40

All JobsIntern Asic Design Engineer JobsIntern Asic Design Engineer Jobs in Riverside, CA

Intern Asic Design Engineer information

See Riverside, CA salary details

$9

$20

$38

How much do intern asic design engineer jobs pay per hour?

As of Sep 2, 2026, the average hourly pay for intern asic design engineer in Riverside, CA is $20.22, according to ZipRecruiter salary data. Most workers in this role earn between $15.05 and $22.55 per hour, depending on experience, location, and employer.

What does an Intern ASIC Design Engineer do?

An Intern ASIC Design Engineer assists in designing, developing, and verifying Application-Specific Integrated Circuits (ASICs) under the guidance of senior engineers. Their responsibilities often include working with hardware description languages like Verilog or VHDL, running simulations, debugging designs, and performing tests to ensure functionality and performance. Interns may also help with documentation, design reviews, and collaborating with cross-functional teams. This role provides hands-on experience in the semiconductor industry and helps build foundational skills for a career in hardware engineering.

What types of projects and responsibilities can I expect as an Intern ASIC Design Engineer?

As an Intern ASIC Design Engineer, you can expect to work on a variety of tasks that support the design and verification of integrated circuits. Typical responsibilities include assisting with RTL coding, running simulations, analyzing test results, and documenting design processes. You'll often collaborate closely with senior engineers and cross-functional teams, gaining exposure to state-of-the-art tools and methodologies. This role provides a valuable learning environment where you're encouraged to ask questions, contribute to team discussions, and develop practical skills that are highly valued in the semiconductor industry.

What are the key skills and qualifications needed to thrive as an Intern ASIC Design Engineer, and why are they important?

To thrive as an Intern ASIC Design Engineer, you need a solid background in digital logic design, computer architecture, and a relevant degree in electrical or computer engineering. Familiarity with hardware description languages such as Verilog or VHDL, simulation tools, and EDA software is typically required. Strong analytical thinking, attention to detail, teamwork, and effective communication make an intern stand out in this role. These skills and qualities are crucial for designing reliable, high-performance integrated circuits and collaborating efficiently within engineering teams.

What is the difference between Intern Asic Design Engineer vs Intern Digital Design Engineer?

AspectIntern Asic Design EngineerIntern Digital Design Engineer
CredentialsTypically pursuing or holding a degree in Electrical Engineering or Computer EngineeringTypically pursuing or holding a degree in Electrical Engineering or Computer Engineering
Work EnvironmentDesign teams focused on ASIC development, hardware design labs, collaborative projectsDigital circuit design, simulation, verification, and hardware testing environments
Industry UsageUsed in semiconductor companies, integrated circuit design firms, and hardware startupsCommon in semiconductor, electronics, and hardware development companies

Both roles involve working on digital hardware design, often requiring similar educational backgrounds. The main difference lies in the focus: Intern Asic Design Engineers work on the overall ASIC development process, while Intern Digital Design Engineers focus specifically on digital circuit design and verification. Both positions are essential in hardware development and often overlap in skills and work environment.

What cities near Riverside, CA are hiring for Intern Asic Design Engineer jobs?

Cities near Riverside, CA with the most Intern Asic Design Engineer job openings:

Intern Asic Design Engineer jobs near you
Infographic showing various Intern Asic Design Engineer job openings in Riverside, CA as of August 2026, with employment types broken down into 33% Internship, 34% Full Time, and 33% Part Time. Highlights an 100% In-person job distribution, with an average salary of $42,048 per year, or $20.2 per hour.

Sr. RTL Design Engineer (Silicon Engineering)

SpaceX

Irvine, CA

$165K - $260K/yr

Full-time

Medical, Dental, Vision, Life, Retirement, PTO

Re-posted 25 days ago

SpaceX rating

8.7

Company rating: 8.7 out of 10

Based on 150 frontline employees who took The Breakroom Quiz

16th of 72 rated aerospace companies

Job description

SR. RTL DESIGN ENGINEER (SILICON ENGINEERING) 

At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe. 

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.   

RESPONSIBILITIES:

  • Evaluate architectural trade-offs based on features, performance requirements and system limitations
  • Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level and deliver the fully verified, synthesis/timing clean design
  • Work closely with verification team to ensure all aspects of the design are covered and verified
  • Provide timing constraint for those IPs and support the physical implementation team (synthesis, timing closure, formality check)
  • Participate in silicon bring-up and validation

BASIC QUALIFICATIONS:

  • Bachelor's degree in electrical engineering, computer engineering, or computer science
  • 5+ years of experience in RTL implementation

PREFERRED SKILLS AND EXPERIENCE:

  • Ability to solve complex problems including clock domain crossings and power optimization
  • ASIC/SoC system integration experience
  • Experience with embedded CPU subsystems
  • Experience with standard bus protocols (e.g. AXI, AHB, etc.)
  • Experience with high speed and low power design techniques
  • Scripting skills (e.g. Python, etc.)
  • Experience with EDA tools such as HDL simulators and HDL Lint tools
  • Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
  • Enjoys being challenged and learning new skills

ADDITIONAL REQUIREMENTS:

  • Ability to work extended hours or weekends as needed for mission critical deadlines

COMPENSATION & BENEFITS:    

Pay range:
ASIC Design Engineer/Senior: $165,000.00 - $260,000.00/per year    
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

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About SpaceX

Sourced by ZipRecruiter

Industry

Aerospace product and parts manufacturing, data services, guided missile and space vehicle manufacturing and satellite telecommunications

Company size

1,001 - 5,000 Employees

Headquarters location

Hawthorne, CA, US

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