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Intern Analog Layout Design Engineer Jobs in Suffield, CT

Quest Global

Physical Design Lead Engineer

Windsor, CT

$130K - $160K/yr

  • Medical

  • Retirement

  • PTO

Physical Design Lead Engineer Location: 175 Addison Rd, Entrance A, Windsor, CT 06095 and ... Work on Physical Verification (PV) , Design Rule Check (DRC) , Layout Versus Schematic (LVS ...

Quest Global

Physical Design Lead Engineer

Windsor, CT · On-site

$130K - $160K/yr

  • Medical

  • Retirement

  • PTO

Physical Design Lead Engineer Location: 175 Addison Rd, Entrance A, Windsor, CT 06095 and ... Work on Physical Verification (PV) , Design Rule Check (DRC) , Layout Versus Schematic (LVS ...

Dennis Group

Electrical Engineer Intern

Springfield, MA · On-site

$18.50 - $24.25/hr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

... layout drawings, one-line, riser, schedules, details, and specifications. * CAD - add 2D devices to ... Sophomore, Junior or Senior pursuing a bachelor's degree in electrical engineering or related field.

Quest Global

Physical Design Lead Engineer

Windsor, CT · On-site

$130K - $160K/yr

  • Medical

  • Retirement

  • PTO

Physical Design Lead Engineer Location: 175 Addison Rd, Entrance A, Windsor, CT 06095 and ... Work on Physical Verification (PV) , Design Rule Check (DRC) , Layout Versus Schematic (LVS ...

Dennis Group

Electrical Engineer Intern

Springfield, MA · On-site

$19 - $25/hr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

... layout drawings, one-line, riser, schedules, details, and specifications. * CAD - add 2D devices to ... Sophomore, Junior or Senior pursuing a bachelor's degree in electrical engineering or related field.

Dennis Group Inc

Architect Intern

Springfield, MA

$22.50/hr

As a design build engineering firm and general contractor, Dennis Group's Architects support our ... As an Architect Intern on the Dennis Group team responsibilities include, but not limited to:

New

Stone Peak

Process Piping Designer

Springfield, MA · On-site

Equipment Layout Design - 2D and 3D. * Platform Design - Conceptual design for review by Structural Engineer. * Piping and Instrumentation Drawing - Understanding of and ability to create, must be ...

TRC Companies, Inc.

Electrical Engineer IV

Windsor, CT · On-site

$117K - $150K/yr

  • Medical

  • Dental

  • Vision

  • Retirement

  • PTO

Main responsibilities include creating electrical protection control and/or physical layout design ... Senior Engineers are expected to be familiar with the following aspects of the typical electrical ...

Dennis Group

Architect Intern

Springfield, MA · On-site

$22.50/hr

  • Medical

  • Dental

  • Vision

  • Life

  • Retirement

  • PTO

As a design build engineering firm and general contractor, Dennis Group's Architects support our ... As an Architect Intern on the Dennis Group team responsibilities include, but not limited to:

New

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Showing results 41-60

All JobsIntern Analog Layout Design Engineer JobsIntern Analog Layout Design Engineer Jobs in Suffield, CT

Intern Analog Layout Design Engineer information

See Suffield, CT salary details

$74.8K

$181K

$197.2K

How much do intern analog layout design engineer jobs pay per year?

As of Aug 19, 2026, the average yearly pay for intern analog layout design engineer in Suffield, CT is $180,954.00, according to ZipRecruiter salary data. Most workers in this role earn between $196,300.00 and $196,300.00 per year, depending on experience, location, and employer.

What is the difference between Intern Analog Layout Design Engineer vs Intern Digital Layout Design Engineer?

AspectIntern Analog Layout Design EngineerIntern Digital Layout Design Engineer
Required SkillsAnalog circuit fundamentals, layout design, SPICE simulationDigital circuit fundamentals, RTL design, layout automation tools
Work EnvironmentDesign teams focused on analog/mixed-signal ICsDesign teams focused on digital ICs and FPGA/ASIC design
Industry UsageSemiconductor companies, chip design firmsSemiconductor companies, FPGA/ASIC vendors

Intern Analog Layout Design Engineers focus on analog/mixed-signal IC layout, requiring knowledge of analog circuits and layout tools. Intern Digital Layout Design Engineers work on digital ICs, emphasizing digital design principles and automation. Both roles are common in semiconductor industries but differ in technical focus and tools used.

Intern Analog Layout Design Engineer jobs near you
Infographic showing various Intern Analog Layout Design Engineer job openings in Suffield, CT as of August 2026, with employment types broken down into 87% Full Time, 8% Part Time, and 5% Contract. Highlights an 84% Physical, 5% Hybrid, and 11% Remote job distribution, with an average salary of $180,954 per year, or $87 per hour.

Physical Design Lead Engineer

Quest Global

Windsor, CT

$130K - $160K/yr

Full-time

Medical, Retirement, PTO

Posted 7 days ago

Quest Global rating

7.8

Company rating: 7.8 out of 10

Based on 11 frontline employees who took The Breakroom Quiz

243rd of 449 rated engineering

Job description

Job Requirements

Company: Quest Global Services-N.A., Inc.

Position Title: Physical Design Lead Engineer

Location: 175 Addison Rd, Entrance A, Windsor, CT 06095 and unanticipated client

locations throughout the U.S.

Position Responsibilities: 

Implement complex design in physical design flow from netlist to GDSII. Work on TSMC advanced process nodes (3nm or below). Take care of floor-planning, CTS (Clock Tree Synthesis), Route use ICC2, Innovus tools related to Cadence and Synopsys. Optimize design with multi-corner multi-mode (MCMM) timing constraint. Fix setup, hold, transition, capacitance, crosstalk violation, min pulse width (MPW), signal EM (Electromigration)

and solving congestion, short, skew, etc. Work on high-speed and complicated clock structure designs with a large number of memories and instances. Use PrimeTime to check and debug timing. Analyze floorplan to reduce congestion using advanced scripting techniques generate a robust clock tree by analyzing the sync points and achieving low latency and minimal power. Work on Static Timing Analysis (STA), Logic Equivalence Checks (LEC), Extraction, Noise, Power. Control timing budgets between blocks & the top-level chip using timing models such as ETM, ILM. Build ECO environments for place and route tools to fix all timing violations. Work on

Power Analysis and IR Drop Analysis to meet the requirements. Work on Physical Verification

(PV) , Design Rule Check (DRC) , Layout Versus Schematic (LVS), Antenna, Electrical Rule

Check (ERC), Design for Manufacturing (DFM). Work on logic equivalence check (LEC) for Pre-

Post Place and Route design.

Position Requirements: 

Bachelor’s degree (or foreign equivalent) in Electronics Engineering, or a

related field, PLUS five (5) years of experience in the job offered or a related position. Experience

must include demonstrable knowledge of: The full Place & Route design flow incl. logical

synthesis, STA, DFT, Placement, Clock Tree Synthesis & physical verification; hardening highspeed,

low power CPU designs; design of large SOC full chip & block level P&R using advance

Process technologies: advanced process nodes (3nm or below); high-speed interfaces at chip level;

clock tree creation incl. sync points & achieving low latency & minimal power; design w/ multicorner

multi-mode timing constraints; STA; control of timing budget between blocks & chip using

timing model such as ETM, ILM; ECO environments for place & route tools to fix timing

violations. Travel to unanticipated client locations throughout the U.S., approximately 30%, as

required. May telecommute from any location within the U.S.

Apply at careers.quest-global.com and reference Job Code 28290.0330

Pay Range: $130,333 - $160,000

Compensation decisions are made based on factors including experience, skills, education, and other job-related factors, in accordance with our internal pay structure. We also offer a comprehensive benefits package, including health insurance, paid time off, and retirement plan.


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