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Image Sensor Analog Design Engineer Jobs in Oregon

Stem Xpert

Mask Design Engineer

Hillsboro, OR · On-site

... strategy, design, software engineering and systems integration. Our tightly integrated offerings ... Analog and Mixed Signal blocks such as LDO, Switching Regulators, Data Converters, PLL, SerDes ...

Intel

Silicon Packaging Design Engineer

Hillsboro, OR

$148K/yr

Intel seeks a motivated and innovative Silicon Packaging Design Engineer to join our team, driving ... experience with Analog/Mixed Signal fundamentals for signal integrity assessments and I/O ...

Analog Devices

Staff PDK Engineer

Beaverton, OR · On-site

... the design and manufacturing of analog, mixed signal and power management products in ADI ... As a PDK developer, you will be expected to possess the necessary programming skills and circuit ...

Addium Inc

Senior Electrical Engineer

Portland, OR · On-site

$130K - $140K/yr

Senior Electrical Engineer Department: Product Development: Hardware Reports To: Director of ... Lead system design efforts across analog/mixed-signal circuits, low-noise sensor front-ends, and ...

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Image Sensor Analog Design Engineer information

What does an image sensor analog design engineer do?

An Image Sensor Analog Design Engineer is responsible for designing and developing the analog circuits within image sensors, which are used in devices like cameras, smartphones, and industrial equipment. Their work involves creating circuits for pixel arrays, amplifiers, analog-to-digital converters, and other components that capture and process light into electronic signals. They collaborate with cross-functional teams to ensure the sensor meets performance, power, and reliability requirements. This role requires expertise in analog circuit design, semiconductor technology, and often involves simulation and testing of prototypes.

What are some common challenges faced by image sensor analog design engineers, and how can they be addressed?

Image Sensor Analog Design Engineers often encounter challenges related to minimizing noise, achieving high dynamic range, and optimizing power consumption in compact layouts. Balancing these factors while ensuring sensor reliability and manufacturability requires close collaboration with cross-functional teams, such as digital designers and process engineers. Staying updated with the latest semiconductor technologies and simulation tools can help in overcoming these hurdles, as well as engaging in peer design reviews to catch potential issues early in the development cycle.

What are the key skills and qualifications needed to thrive as an image sensor analog design engineer, and why are they important?

To thrive as an Image Sensor Analog Design Engineer, you need a strong background in analog circuit design, semiconductor physics, and experience with CMOS image sensor technology, typically supported by a degree in electrical engineering or a related field. Familiarity with industry-standard EDA tools like Cadence, SPICE simulators, and layout verification software, as well as knowledge of design for manufacturability, is essential. Strong problem-solving ability, attention to detail, and effective communication are critical soft skills that help in collaborating with cross-functional teams and troubleshooting complex design issues. These skills ensure the development of high-performance, reliable image sensors that meet demanding technical and market requirements.

What are popular job titles related to Image Sensor Analog Design Engineer jobs in Oregon?

For Image Sensor Analog Design Engineer jobs in Oregon, the most frequently searched job titles are:

What job categories do people searching Image Sensor Analog Design Engineer jobs in Oregon look for?

The top searched job categories for Image Sensor Analog Design Engineer jobs in Oregon are:

What cities in Oregon are hiring for Image Sensor Analog Design Engineer jobs?

Cities in Oregon with the most Image Sensor Analog Design Engineer job openings:

Image Sensor Analog Design Engineer jobs near you
Infographic showing various Image Sensor Analog Design Engineer job openings in Oregon as of July 2026, with employment types broken down into 92% Full Time, 5% Part Time, 2% Contract, and 1% Nights. Highlights an 89% Physical, 3% Hybrid, and 8% Remote job distribution.

Mixed Signal Logic Design Engineer

Intel

Hillsboro, OR

Full-time

Medical, Retirement, PTO

Re-posted 15 days ago

Intel rating

8.7

Company rating: 8.7 out of 10

Based on 147 frontline employees who took The Breakroom Quiz

19th of 157 rated electronics manufacturers

Job description

Job Details:Job Description: 

Position Overview

Develops the logic design, register transfer level (RTL) coding, and simulation for mixed-signal IPs required to generate cell libraries, functional units, IP blocks, and subsystems for integration in full chip designs. Participates in the definition of architecture and microarchitecture features of the block being designed.

Applies various strategies, tools, and methods for mixed-signal designs including analog behavior modeling and circuit simulation to write RTL and optimize mixed-signal logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.

Reviews the verification plan and implementation to ensure design features are verified correctly, and resolves and implements corrective measures for failing RTL tests to ensure correctness of features. Supports SoC customers to ensure high quality integration of the IP block.

Key Responsibilities

  • Develop logic design, RTL coding, and simulation for mixed-signal IPs including cell libraries, functional units, IP blocks, and subsystems
  • Participate in the definition of architecture and microarchitecture features of the block being designed
  • Apply strategies, tools, and methods for mixed-signal designs including analog behavior modeling and circuit simulation
  • Write and optimize mixed-signal logic to meet power, performance, area, and timing goals
  • Ensure design integrity for physical implementation
  • Review verification plans and implementation to confirm design features are verified correctly
  • Resolve and implement corrective measures for failing RTL tests to ensure feature correctness
  • Support SoC customers to ensure high-quality integration of the IP block

What We're Looking For

To be successful in this role, you should demonstrate the following professional traits:

  • Cross-functional collaboration- ability to work effectively with analog, digital, and physical design teams throughout the design cycle
  • Ownership mentality- capable of independently designing and owning mixed-signal subsystems and IP blocks end-to-end
  • Strong debugging instincts- skilled at identifying and resolving issues across both analog and digital domains with precision and efficiency
Qualifications:

Minimum Qualifications

You must possess one of the following education and experience combinations to be initially considered for this position:

  • Bachelor's Degree in Electrical Engineering, Computer Science, Electronics and Communications Engineering, or related field with7+ yearsof industry experience, OR
  • Master's Degree in Electrical Engineering, Computer Science, Electronics and Communications Engineering, or related field with4+ yearsof industry experience

In addition, all candidates must have:

  • Expert-level proficiency in Verilog / SystemVerilog (RTL design)
  • Digital logic fundamentals
  • Experience integrating analog IP with digital logic
  • Deep knowledge of RTL-to-GDSII flow, STA, and CDC
  • Familiarity with EDA tools
  • Understanding of timing, power, and performance trade-offs

Preferred Qualifications

  • Knowledge of Power Delivery and Power Management systems
  • Solid understanding of analog/mixed-signal blocks such as ADCs, DACs, PLLs, and regulators
  • DFT as it relates to mixed-signal HIP
  • Scripting language experience, including Perl, TCL/Tk, or Python
  • Experience with mixed-signal simulation
  • Strong debugging skills across analog and digital domains
Job Type:Experienced HireShift:Shift 1 (United States of America)Primary Location: US, Oregon, HillsboroAdditional Locations:US, California, Santa Clara, US, Massachusetts, Beaver Brook, US, Texas, AustinBusiness group:The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses.Posting Statement:All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.Position of TrustN/ABenefits

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Find out more about the benefits of working at Intel.

Annual Salary Range for jobs which could be performed in the US: $164,470.00-232,190.00 USDThe range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific compensation range for your preferred location during the hiring process.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

*

ADDITIONAL INFORMATION: Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter.

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About Intel

Sourced by ZipRecruiter

Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore's Law to bring smart, connected devices to every person on Earth

Industry

Manufacturing

Company size

10,000+ Employees

Headquarters location

Santa Clara, CA, US

Year founded

1968

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