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High Performance Cpu Rtl Design Engineering Jobs

Tenstorrent

Sr. Engineer, CPU RTL Design

Austin, TX · On-site

$100K - $500K/yr

Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and ... We are looking for a talented engineer to join our CPU design team to define and implement RTL for ...

Qualcomm

CPU Systems RTL Engineer

Santa Clara, CA · On-site

$117K - $160K/yr

We are hiring talented engineers for CPU RTL development targeted for high performance, low power ... meets the performance goals. * Design delivery. Work with multi-functional engineering team to ...

Qualcomm

CPU RTL LLC Engineer

Santa Clara, CA · On-site

We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices in the cache and memory controller design. As a CPU Micro-architecture and RTL Design ...

Qualcomm

RISCV CPU System RTL Engineer

Santa Clara, CA · On-site

$142K - $213K/yr

... high-performance, low-power devices. In this role you will contribute to architecture and product ... Deliver design: collaborate with cross‑functional engineering teams to validate physical design ...

Qualcomm

RISCV CPU System RTL Engineer

Santa Clara, CA · On-site

$117K - $160K/yr

Engineering Group, Engineering Group > CPU Engineering General Summary: We are hiring talented ... Knowledge of high-performance design strategies and trade-offs in CPU microarchitecture

Qualcomm

CPU Micro-architect/RTL Designer

Austin, TX · On-site

$211K - $317K/yr

We are hiring talented engineers for CPU RTL development targeted for high performance, low power devices. As a CPU Micro-architecture and RTL Design Engineer, you will work with chip architects to ...

SiFive, Inc.

WI · On-site

$124K - $152K/yr

You will work closely with architecture, RTL, performance, and verification teams to ensure design ... Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or ...

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High Performance Cpu Rtl Design Engineering information

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$88.2K

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How much do high performance cpu rtl design engineering jobs pay per year?

As of Sep 10, 2026, the average yearly pay for high performance cpu rtl design engineering in the United States is $88,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $68,000.00 and $98,500.00 per year, depending on experience, location, and employer.

What are popular job titles related to High Performance Cpu Rtl Design Engineering jobs?

For High Performance Cpu Rtl Design Engineering jobs, the most frequently searched job titles are:

Infographic showing various High Performance Cpu Rtl Design Engineering job openings in the United States as of August 2026, with employment types broken down into 1% As Needed, 80% Full Time, 16% Part Time, and 3% Contract. Highlights an 90% Physical, 1% Hybrid, and 9% Remote job distribution, with an average salary of $88,150 per year, or $42.4 per hour.

Staff Engineer CPU design, RTL , Physical Design (PD)

San Diego, CA • On-site

Info Way Solutions
IT Services • 51 - 200 employees
Learn more about Info Way Solutionsexternal

$144K - $148K/yr

Other

Posted 2 days ago

New

Job description

Job Summary

Qualcomm is seeking a highly skilled Staff Engineer with strong experience in CPU design, RTL development, and/or Physical Design (PD) to work on next-generation high-performance, low-power SoCs and CPU architectures.

The ideal candidate will have hands-on experience in ASIC/SoC development, strong understanding of CPU microarchitecture and digital design, and the ability to work across RTL, synthesis, physical implementation, timing, power, and area optimization. The engineer will collaborate closely with Architecture, RTL, Design Verification, Physical Design, DFT, CAD, Power, and Post-Silicon teams.

Key Responsibilities

  • Design and optimize high-performance CPU/SoC blocks from microarchitecture through RTL and physical implementation.
  • Develop, review, and refine Verilog/SystemVerilog RTL.
  • Participate in microarchitecture definition and design trade-offs targeting Power, Performance, and Area (PPA).
  • Work closely with Physical Design teams on synthesis, floorplanning, placement, CTS, routing, timing closure, and signoff.
  • Analyze and resolve timing, congestion, power, area, and design-closure issues.
  • Support RTL-to-GDS implementation and identify RTL changes required for physical convergence.
  • Perform or support STA/MMMC analysis, constraint development, and timing optimization.
  • Collaborate with verification teams on functional verification, coverage, debugging, and design quality.
  • Work with DFT, CAD, and implementation teams to resolve complex design issues.
  • Develop automation and productivity solutions using Python, Tcl, Perl, or Shell.
  • Participate in design reviews and provide technical leadership on critical design problems.
  • Mentor junior engineers and contribute to methodology and flow improvements.

Required Qualifications

  • Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
  • 4–10 years of experience in ASIC/SoC, CPU, RTL, or Physical Design.
  • Strong understanding of digital design and ASIC development flows.
  • Hands-on experience with Verilog/SystemVerilog.
  • Strong understanding of CPU/microprocessor architecture is highly preferred.
  • Experience with one or more of:
    • RTL design
    • Logic design
    • Synthesis
    • Physical Design
    • Static Timing Analysis
    • Timing closure
    • PPA optimization
    • SoC integration
  • Experience working in Linux/Unix environments.
  • Strong scripting/programming skills in Python, Tcl, Perl, or Shell.
  • Strong debugging, analytical, and problem-solving skills.

Preferred Qualifications

CPU / RTL

  • Experience with CPU pipeline architecture, including Fetch, Decode, Rename, Execute, Load/Store, Cache, MMU, or Branch Prediction.
  • Experience with out-of-order execution, memory hierarchy, or processor microarchitecture.
  • Strong RTL coding and microarchitecture implementation experience.
  • Knowledge of CDC, lint, synthesis, formal verification, and low-power design.

Physical Design

  • Experience with complete RTL-to-GDSII flow.
  • Floorplanning, power planning, placement, CTS, routing, and timing closure.
  • Experience with Cadence Innovus and/or Synopsys Fusion Compiler.
  • Experience with PrimeTime STA.
  • MMMC timing analysis and advanced-node implementation.
  • Experience with IR drop, EM, signal integrity, crosstalk, ECOs, and physical verification.
  • Knowledge of UPF and low-power implementation.

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