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Hardware Accelerator Design Engineer Jobs (NOW HIRING)

OMNIVISION

SoC Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

Work with algorithm engineers for module level design, including hardware C model implementation ... accelerators. * Design tools, such as microarchitecture simulators, RTL synthesis tools, and ...

OMNIVISION

SoC Design Engineer

Santa Clara, CA · On-site

$156K - $160K/yr

Work with algorithm engineers for module level design, including hardware C model implementation ... accelerators. * Design tools, such as microarchitecture simulators, RTL synthesis tools, and ...

OMNIVISION

SoC Design Engineer

Santa Clara, CA · On-site

Work with algorithm engineers for module level design, including hardware C model implementation ... accelerators. * Design tools, such as microarchitecture simulators, RTL synthesis tools, and ...

Nvidia

ASIC Design Efficiency Engineer

Durham, NC · On-site

NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and processors on our next-generation mobile, embedded and datacenter platforms. This position offers the ...

Nvidia

ASIC Design Efficiency Engineer

Austin, TX · On-site

NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and processors on our next-generation mobile, embedded and datacenter platforms. This position offers the ...

Nvidia

ASIC Design Efficiency Engineer

Austin, TX · On-site

NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and processors on our next-generation mobile, embedded and datacenter platforms. This position offers the ...

Neuralink

Digital IC Design Engineer

Austin, TX · On-site

$116K - $233K/yr

Our Digital IC Design Engineer will be responsible for delivering micro-architecture and register ... Low-power general-purpose hardware accelerators * Low-power graphics processing units * Low-power ...

Nvidia

ASIC Design Efficiency Engineer

Durham, NC · On-site

NVIDIA is seeking extraordinary methodology engineers to design hardware accelerators and processors on our next-generation mobile, embedded and datacenter platforms. This position offers the ...

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Hardware Accelerator Design Engineer information

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$69.5K

$147.5K

$215K

How much do hardware accelerator design engineer jobs pay per year?

As of Sep 10, 2026, the average yearly pay for hardware accelerator design engineer in the United States is $147,512.00, according to ZipRecruiter salary data. Most workers in this role earn between $120,000.00 and $174,000.00 per year, depending on experience, location, and employer.

What are popular job titles related to Hardware Accelerator Design Engineer jobs?

For Hardware Accelerator Design Engineer jobs, the most frequently searched job titles are:

Infographic showing various Hardware Accelerator Design Engineer job openings in the United States as of August 2026, with employment types broken down into 90% Full Time, 7% Part Time, and 3% Contract. Highlights an 81% Physical, 5% Hybrid, and 14% Remote job distribution, with an average salary of $147,512 per year, or $70.9 per hour.

SoC Design Engineer

Santa Clara, CA • On-site

OMNIVISION
Software Development • 1 - 5K employees
Learn more about OMNIVISIONexternal

$156K - $160K/yr

Full-time

Re-posted 5 days ago

Job description

Job Title: SoC Design Engineer
 
Job Duties:  
 
Be responsible for digital design of ASIC cores within image sensor SoC products, including IP design, analysis, integration, and validation. Collaborate with physical design teams on floor-planning, timing closure, and DFT implementation. Conduct timing control logic design and static timing analysis (STA) for sensor interfaces and mixed-signal integration. Perform chip bring-up, validation and debugging. Design, integrate and validate data pipeline according to PRD/design specification and system architecture of SoC products, following ASIC design flow: coding, simulation, synthesis, static timing analysis, formality verification, DFT, using Simvision, EDA tools such as Prime Time, cadence Virtuoso, Design Compiler, Integrator, and Verilog and System Verilog programming languages etc. Conduct design verification and modeling using SVA, Python, Perl, C++/C, and HLS. Work with digital and analog engineers for system design, integration and validation. Work with algorithm engineers for module level design, including hardware C model implementation, micro architecture design, RTL design and hardware/software co-simulation. Work with algorithm and application engineers for project-based microarchitecture improvements. Conduct silicon validation, debugging and tuning.
 
Requirements:
 
Master’s degree or foreign equivalent degree in Electrical Engineering, Computer Engineering, or a related field.
 
Required skills and/or academic training in the following: 
 
  • Arithmetic circuit design related to general datapath circuits, ML and AI circuits.
  • Arithmetic circuit design, timing analysis; synchronous and asynchronous FSMs; power, test, and debug.
  • Design and design debug with System Verilog; Logic design and analysis.  
  • Processing Subsystem, including superscalar out-of-order cores, multicore and heterogeneous processors, and purpose-specific accelerators.  
  • Design tools, such as microarchitecture simulators, RTL synthesis tools, and modeling for area, power, and thermal. 
  • FPGA platforms to compute acceleration.  
  • FPGAs technology, architecture and applications.  
  • Register-Transfer Level (RTL) hardware design.  
  • Planning and specification, writing Verilog models, and designing custom circuits and synthesized standard cell blocks.  
  • Using industrial CAD tools and flows for digital, analog/RF, or mixed-signal chip design.  
  • Full-chip integration and verification for tapeout.  
 
Annual base salary for this role in California, US is expected to be between $156,853 - $160,000. Actual pay will be determined on a number of factors such as relevant skills and experience, and the pay of employees in the similar role.
 

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