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Hardware Acceleration Engineer Jobs (NOW HIRING)

Brooks Automation, Inc.

Senior FPGA Programmer

Chelmsford, MA · On-site

$135K - $173K/yr

... FPGA Engineer to lead the architecture, development, and implementation of advanced FPGA-based ... Hardware acceleration of computationally intensive algorithms The ideal candidate combines deep ...

Brooks Automation

Senior FPGA Programmer

Chelmsford, MA · On-site

$135K - $173K/yr

... FPGA Engineer to lead the architecture, development, and implementation of advanced FPGA-based ... Hardware acceleration of computationally intensive algorithms The ideal candidate combines deep ...

Apple

ANE Pre-Silicon Driver Engineer

Sunnyvale, CA · On-site

Description In our ANE software team, we are dedicated to providing hardware acceleration using the ... programming skills in C, C++ or Python Preferred Qualifications MS or PhD in computer science ...

Whoop

Android Engineer II (Hardware Accelerate)

Boston, MA · On-site

$125K - $175K/yr

WHOOP is hiring a Software Engineer II to join the Hardware Accelerate team, focusing on Android development. In this role, you will help design, build, and optimize Android modules that interface ...

Brinc Drones Inc

Principal FPGA Engineer

Seattle, WA · On-site

$110K - $250K/yr

BRINC is recruiting exceptional engineers to build the next generation of autonomous emergency ... General experience with hardware acceleration of algorithms on modern GPU architectures.

Augusta Hitech

$82K - $97K/yr

Optimize deep learning models for edge deployment using hardware acceleration to meet strict cycle ... Required Programming Languages C++: Essential for writing highly optimized, multithreaded ...

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Hardware Acceleration Engineer information

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$51K

$146.2K

$196.5K

How much do hardware acceleration engineer jobs pay per year?

As of Sep 10, 2026, the average yearly pay for hardware acceleration engineer in the United States is $146,230.00, according to ZipRecruiter salary data. Most workers in this role earn between $123,500.00 and $163,000.00 per year, depending on experience, location, and employer.

What is a hardware acceleration engineer?

A Hardware Acceleration Engineer is a specialist who designs, develops, and optimizes hardware components or systems to perform specific computational tasks more efficiently than general-purpose processors. They work with technologies like FPGAs, GPUs, or ASICs to accelerate workloads such as machine learning, video processing, or data encryption. Their role often involves close collaboration with software and hardware teams to identify bottlenecks and implement solutions that improve overall system performance.

What are the key skills and qualifications needed to thrive as a hardware acceleration engineer?

To thrive as a Hardware Acceleration Engineer, you need a strong background in computer engineering, digital logic design, and familiarity with hardware description languages (HDLs) like VHDL or Verilog, often supported by a relevant engineering degree. Experience with FPGA/ASIC development tools, hardware simulation environments, and knowledge of acceleration frameworks such as CUDA or OpenCL is typically required. Strong problem-solving skills, attention to detail, and effective teamwork set outstanding candidates apart in this field. These skills and qualities are crucial for designing efficient, high-performance hardware solutions that meet complex computational demands.

How does a hardware acceleration engineer typically collaborate with software development teams?

Hardware Acceleration Engineers work closely with software development teams to identify performance bottlenecks and design custom hardware solutions, such as FPGA or ASIC implementations, that optimize computational tasks. This collaboration often involves frequent code reviews, joint architecture discussions, and iterative testing to ensure seamless integration between hardware and software components. Effective communication and a strong understanding of both hardware and software constraints are essential to deliver high-performance, scalable systems.

What cities are hiring for Hardware Acceleration Engineer jobs?

Cities with the most Hardware Acceleration Engineer job openings:

What states have the most Hardware Acceleration Engineer jobs?

States with the most job openings for Hardware Acceleration Engineer jobs include:

What are popular job titles related to Hardware Acceleration Engineer jobs?

For Hardware Acceleration Engineer jobs, the most frequently searched job titles are:

Infographic showing various Hardware Acceleration Engineer job openings in the United States as of July 2026, with employment types broken down into 2% As Needed, 73% Full Time, 18% Part Time, 1% Contract, and 6% Nights. Highlights an 77% Physical, 3% Hybrid, and 20% Remote job distribution, with an average salary of $146,230 per year, or $70.3 per hour.

Staff AI Inference and Acceleration Engineer

San Jose, CA • On-site

Figure
See more jobs at Figureexternal

$180K - $275K/yr

Full-time

Re-posted 15 days ago

Key responsibilities

  • Own the on-board inference architecture by mapping models to available accelerators based on latency, power, and memory budgets.

  • Partition inference workloads across heterogeneous compute resources to balance real-time performance with power and thermal constraints.

  • Optimize inference toolchains end-to-end, including model export, runtime execution, and applying compression techniques to reduce compute, memory, and power footprint.

Job description

Figure is an AI robotics company developing autonomous general-purpose humanoid robots. The goal of the company is to ship humanoid robots with human level intelligence. Its robots are engineered to perform a variety of tasks in the home and commercial markets. Figure is headquartered in San Jose, CA.
We are looking for a Staff AI Inference & Acceleration Engineer to join the Platform Software team and own the on-board inference architecture for Figure's humanoid robots. You will be the technical authority on how AI workloads are mapped, optimized, and executed across the robot's compute hardware - driving down power consumption and cost while meeting the strict latency and reliability demands of a real-time autonomous system.
Responsibilities:
  • Own the on-board inference architecture - mapping models to available accelerators (NPU, GPU, DSP, CPU) based on latency, power, and memory budgets.
  • Partition inference workloads across heterogeneous compute resources, balancing real-time performance with power and thermal constraints.
  • Define and maintain a system-level compute budget across all inference tasks running on the robot.
  • Evaluate next-generation acceleration hardware and contribute to the definition of future compute platform requirements.
  • Optimize inference toolchains end-to-end - from model export through runtime execution - for target hardware.
  • Apply quantization (INT8, INT4, mixed-precision), pruning, operator fusion, and other compression techniques to reduce compute, memory, and power footprint.
  • Profile inference pipelines to identify and eliminate bottlenecks in latency, memory bandwidth, and power consumption.
  • Optimize kernel scheduling, memory layout, and data movement across the compute hierarchy.
  • Partner closely with the AI/ML team to define model architecture constraints that are hardware-friendly from the outset.
  • Work with the Platform Software team on runtime integration, scheduling, and power management.
  • Engage with silicon vendors and research teams to track the accelerator landscape and influence hardware roadmaps.

Requirements:
  • M.S. or Ph.D. in Computer Engineering, Electrical Engineering, Computer Science, or a related field - or equivalent industry experience.
  • At least 8 years of industry experience in hardware acceleration, ML systems, or compute architecture.
  • Deep understanding of AI/ML inference - model formats (ONNX, TFLite, etc.), inference runtimes, and deployment pipelines.
  • Hands-on experience optimizing models for edge or embedded hardware using quantization, pruning, and operator-level tuning.
  • Strong understanding of computer architecture - memory hierarchies, data movement, and heterogeneous compute.
  • Experience profiling and benchmarking inference workloads across CPU, GPU, NPU, DSP.
  • Familiarity with low-level toolchains and compilation frameworks (e.g. TVM, MLIR, TensorRT, Torch, SNPE/QNN, JAX, CUDA, ROCm).
  • Solid software engineering skills in C++ and Python.
  • Strong cross-functional communication skills - able to work effectively across hardware, software, and AI/ML teams.

Bonus Qualifications:
  • Knowledge of real-time operating constraints and their impact on inference scheduling.
  • Track record of co-designing model architectures with ML teams to meet hardware constraints.

The US base salary range for this full-time position is between $180,000 - $275,000 annually.
The pay offered for this position may vary based on several individual factors, including job-related knowledge, skills, and experience. The total compensation package may also include additional components/benefits depending on the specific role. This information will be shared if an employment offer is extended.

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