Google Tpu Jobs (NOW HIRING)

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 2 years of experience with RTL Design.
• Experience with digital design, including synchronous and asynchronous logic, state machines, and bus protocols.
• Experience optimizing designs for performance, power or area.
• Experience collaborating cross-functionally with DV teams on test plan creation and execution.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with CDC, RDC, RTL Linting and LEC.
• Experience with scripting languages (i.e. Tcl, Python or Perl).
• Experience architecting RTL solutions.

About the job
In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As an RTL Design Engineer on the Tensor Processing Units (TPU) team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your expertise in digital logic design, computer architecture, and RTL coding to create innovative and efficient hardware solutions. You will be responsible for the microarchitecture, design, and implementation of key digital logic blocks within the TPU. Your role requires collaborating with cross-functional teams, including Verification, Physical Design, Validation, and Firmware, to deliver hardware. You will own critical design deliverables and contribute to the continuous improvement of our design methodologies and flows.
This position offers the opportunity to manage technical problems at the forefront of AI hardware, working in a dynamic and collaborative environment.
The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
The US base salary range for this full-time position is $138,000-$198,000 bonus equity benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.
Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google .
Responsibilities

• Define and document the microarchitecture for digital designs within the TPU.
• Develop high-quality, performant, and power-efficient Register Transfer Level (RTL) code, primarily in SystemVerilog.
• Collaborate with the verification team to develop test plans, debug RTL, and ensure functional correctness.
• Co-ordinate with the physical design team to meet timing, area, power, and manufacturability requirements.
• Contribute to the development and enhancement of design tools, flows, and methodologies.

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