Google Rf Engineer Jobs (NOW HIRING)

Location: Redwood City, California

Compensation: $160,000 - 200,000 USD / year

Array Labs builds advanced radar systems to help humanity understand and respond to changes across the physical world.

We’re launching a coordinated fleet of radar satellites to create a high-resolution 3D map of the Earth – updated in real time – enabling faster, smarter decision-making for government and commercial organizations supporting disaster response, infrastructure resilience, and mission‑critical geopolitical intelligence.

We design and build our satellites end‑to‑end, producing the world’s most advanced earth observation satellites. Our fleet will deliver unprecedented levels of accuracy, coverage, and responsiveness to power critical insights precisely where they’re needed most.

About the Job

As a Lead RF PCB Layout Engineer, you will own the physical implementation of Array’s RF and microwave electronics in Altium, translating schematics and performance requirements into layouts that work on the first spin. Your work will include component placement, controlled‑impedance routing, stack‑up definition, grounding and shielding strategy, connector and launch design, and isolation of sensitive RF and mixed‑signal domains.

You will partner closely with RF design, electrical, antenna, mixed‑signal, mechanical, and test engineers to drive layout constraints, reviews, and manufacturing releases. The boards you ship will directly determine RF performance, stability, spurious behavior, and overall sensor reliability in the lab and on orbit.

Responsibilities:

• Own RF PCB layout from initial placement through manufacturing release in Altium Designer
• Define and implement stack-ups, controlled-impedance routing, and RF grounding, shielding, and isolation strategies
• Translate schematic intent into layouts that meet RF performance requirements, including connector launches, transitions, filtering, and protection circuitry placement
• Partner with RF design, electrical, antenna, mixed‑signal, mechanical, and test engineers to develop layout constraints, run reviews, and de-risk first-pass success
• Drive DFM/DFT considerations with fabrication and assembly partners, including documentation and release artifacts

Basic Qualifications:

• B.S. in Electrical Engineering, or a related field with 8+ years of relevant experience
• Experience in PCB layout, fabrication, and release of RF and/or high‑performance electronics
• Excellent teamwork and communication skills
• Learns new concepts rapidly, completely, and in a self‑directed manner
• High levels of self‑motivation and personal accountability
• Ability to work in a fast‑paced environment under significant time constraints

Preferred Skills and Experience:

• Experience designing RF and microwave PCB layouts including controlled‑impedance routing, launches and transitions, grounding, shielding, and isolation
• Comfort with Altium Designer for constraint‑driven layout and clean manufacturing outputs; experience with Allegro and/or OrCAD is a plus
• Experience developing PCB stack-ups and layout constraints for high‑frequency, high‑performance electronics
• A strong intuition for layout‑driven RF behavior, including coupling, return paths, leakage, spurious paths, and stability risks
• Experience working closely with RF design engineers to translate schematic intent into layouts that work on the first spin
• Experience with manufacturing release, DFM/DFT considerations, and collaborating with fabrication and assembly partners
• Experience supporting lab bring‑up and RF characterization alongside design and test engineers (e.g., helping troubleshoot issues seen on VNAs, spectrum analyzers, and in system testing)
• Experience with EM and RF analysis workflows for layout validation (e.g., HFSS, CST, ADS Momentum) is a plus
• Experience taking RF hardware from prototype through qualification and environmental testing

ITAR Requirements:

• To conform to U.S. Government space technology export regulations, including the International Traffic in Arms Regulations (ITAR) you must be a U.S. citizen, lawful permanent resident of the U.S., protected individual as defined by 8 U.S.C. 1324b(a)(3), or eligible to obtain the required authorizations from the U.S. Department of State

Equal Opportunity Employer:

• Array Labs is an Equal Opportunity Employer. Employment decisions are made on the basis of merit, competence, and job qualifications and will not be influenced in any manner by gender, color, race, ethnicity, national origin, sexual orientation, religion, age, gender identity, veteran status, disability status, marital status, mental or physical disability or any other legally protected status

$160,000 - $200,000 a year

Interview Process

We will conduct interviews via Google Meet; the typical process takes around 2‑4 weeks to complete from start to finish.

Hiring and Compensation Strategy

Our hiring and compensation strategy is simple:

1) find uncommonly good people

2) pay them uncommonly well

You can anticipate competitive pay, with high flexibility between salary and equity‑based compensation.

Why Join Array Labs?

Array Labs is launching a constellation of satellites to create the first high-resolution, real‑time, three‑dimensional model of Earth. Our next‑generation satellite technology will offer image quality 60x greater than traditional techniques, profoundly expanding humanity’s ability to understand and respond to events on a global scale.

In forging an affordable, accessible, accurate representation of Earth, our work has the potential to transform the face of dozens of fields, including autonomy, telecommunications, disaster relief, gaming, climate science, defense and construction.