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Google Physical Design Jobs (NOW HIRING)

Google

Staff CPU Physical Design Engineer

Austin, TX · On-site

$134K - $138K/yr

Google's mission is to organize the world's information and make it universally accessible and ... Pioneer novel physical design methodologies, tool flows, and AI/ML optimization techniques to ...

Google Inc.

Staff CPU Physical Design Engineer

Austin, TX · On-site

$134K - $138K/yr

Copy link Google Austin, TX, USA ; Mountain View, CA, USA Advanced Experience owning outcomes and ... Share Staff CPU Physical Design Engineer * Copy link In most instances, this position requires in ...

Google

RTL Design Engineer, TPU and ML

Sunnyvale, CA · On-site

Work closely with the physical design team to meet timing, area, power, and manufacturability requirements. Information collected and processed as part of your Google Careers profile, and any job ...

Google

TPU SoC Design Engineer, Cloud

Sunnyvale, CA · On-site

... Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries ... Physical Design, Verification, Validation, Firmware...) at various project milestones. You will ...

Google Inc.

TPU SoC Design Engineer, Cloud

Sunnyvale, CA · On-site

... Physical Design team to meet timing, area, power, and manufacturability requirements. * Contribute to the development and enhancement of design tools, flows, and methodologies. Google is proud to be ...

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Google Physical Design information

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$95K

$141.5K

How much do google physical design jobs pay per year?

As of Sep 9, 2026, the average yearly pay for google physical design in the United States is $139,408.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $140,000.00 per year, depending on experience, location, and employer.

What is Google Physical Design?

Google Physical Design refers to the process of designing, verifying, and optimizing the physical layout of integrated circuits (ICs), such as those used in Google's hardware products. Physical design engineers at Google are responsible for translating logical circuit designs into layouts that can be manufactured efficiently and reliably. This work includes tasks like floorplanning, placement, routing, timing analysis, and design rule checking, ensuring that chips meet performance, area, and power requirements. Physical design is a critical step in the semiconductor manufacturing process, and at Google, it supports projects like custom silicon for data centers, mobile devices, and more.

What are the key skills and qualifications needed to thrive as a Google Physical Design engineer?

To thrive as a Google Physical Design Engineer, you need a solid background in electrical engineering, digital design, and ASIC/FPGA implementation, typically supported by a relevant degree. Experience with industry-standard EDA tools like Cadence, Synopsys, and Mentor Graphics, as well as knowledge of scripting languages such as TCL and Python, is essential. Strong problem-solving abilities, attention to detail, and effective communication skills help you collaborate with multidisciplinary teams and address design challenges. These skills and qualifications are critical to ensure efficient, high-performance chip designs that meet rigorous industry standards.

What are some common challenges faced by engineers in Google Physical Design roles, and how are they typically addressed?

Engineers in Google Physical Design roles often encounter challenges such as meeting stringent timing and power constraints, managing complex design hierarchies, and ensuring silicon manufacturability. These challenges are typically addressed through close collaboration with cross-functional teams, leveraging advanced EDA tools, and iterative design reviews. Continuous learning and adaptation to rapidly evolving technology nodes are also crucial, as is maintaining effective communication with verification and architecture teams to ensure the final design meets all requirements.

What is the difference between Google Physical Design vs Google Hardware Design?

AspectGoogle Physical DesignGoogle Hardware Design
FocusTranslating circuit schematics into physical layouts for chips and boardsDesigning overall hardware components and systems for devices
SkillsVLSI, CAD tools, circuit layout, fabrication processesElectrical engineering, system architecture, component selection
Work EnvironmentSemiconductor labs, design officesHardware labs, product development teams
CertificationsVLSI design, CAD certificationsElectrical engineering degrees, hardware design certifications

Google Physical Design involves creating the physical layout of integrated circuits, focusing on circuit placement and routing. In contrast, Google Hardware Design encompasses the broader process of designing entire hardware systems and devices. While both roles require electrical engineering knowledge, Physical Design is more specialized in chip-level layout, whereas Hardware Design covers system-level development.

More about Google Physical Design jobs

What job categories do people searching Google Physical Design jobs look for?

The top searched job categories for Google Physical Design jobs are:

Google Physical Design jobs near you
Infographic showing various Google Physical Design job openings in the United States as of September 2026, with employment types broken down into 2% As Needed, 73% Full Time, 20% Part Time, 1% Temporary, 3% Contract, and 1% Nights. Highlights an 96% Physical, 1% Hybrid, and 3% Remote job distribution, with an average salary of $139,408 per year, or $67 per hour.

Staff CPU Physical Design Engineer

Austin, TX • On-site

Google
Software Development • 10K+ employees
Learn more about Googleexternal

$134K - $138K/yr

Full-time

Posted 14 days ago

Google rating

8.8

Company rating: 8.8 out of 10

Based on 103 frontline employees who took The Breakroom Quiz

48th of 247 rated software companies

Job description

info_outline
X In most instances, this position requires in-person interviews as part of the hiring process.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Austin, TX, USA; Mountain View, CA, USA.
Minimum qualifications:
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 10 years of experience in high-performance, low-power physical design implementation or design convergence techniques with custom or industry standard synthesis, PnR and signoff tools.

Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
  • Experience leading cross-functional engineering initiatives across Architecture, RTL, DFT, and Technology partners to optimize sub-system microarchitecture.
  • Understanding of power grid design, EMIR constraints, and low-power implementation techniques.
  • Track record of architecting CPU class physical design methodologies, custom tool enhancements, or AI/ML-assisted PPA optimization flows.

About the job
Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.
Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $192000 - $278000 (USD) 20% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities
  • Lead end-to-end physical design strategy and execution for top-level and critical CPU blocks across advanced process nodes.
  • Pioneer novel physical design methodologies, tool flows, and AI/ML optimization techniques to maximize power, performance, and area (PPA).
  • Resolve complex timing, power grid, electromigration and IR drop (EMIR), and physical verification bottlenecks in tight iteration loops.
  • Drive technical roadmaps, mentor executive engineering peers, and influence architectural trade-offs across cross-functional teams.

Information collected and processed as part of your Google Careers profile, and any job applications you choose to submit is subject to Google's Applicant and Candidate Privacy Policy .
Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity/expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents-to-be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy , Know your rights: workplace discrimination is illegal , Belonging at Google , and How we hire .
If you have a need that requires accommodation, please let us know by completing our Accommodations for Applicants form .
Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting.
To all recruitment agencies: Google does not accept agency resumes. Please do not forward resumes to our jobs alias, Google employees, or any other organization location. Google is not responsible for any fees related to unsolicited resumes.
Equity is granted exclusively and discretionarily by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right.

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