Google Physical Design Jobs (NOW HIRING)

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 4 years of experience with physical design from RTL to Graphic Data System II (GDSII), including synthesis, floor planning, place and route, and timing closure.
• Experience with scripting languages in one or more of the following: Perl, Python, or Tcl.
• Experience working with external partners on physical design (PD) closure.
• Experience with Synopsys/Cadence PnR tools and backend flows (e.g., LEC, PI/SI, DRC/LVS, etc.).

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• 7 years of experience with physical design.
• Experience executing low-power physical design implementation using industry-standard EDA tools (Innovus/FC).
• Experience in sign-off convergence including Static timing analysis (STA), electrical checks, and physical verification.
• Experience in utilizing AI techniques for faster and optimal Physical Design Convergence (e.g., timing, floorplanning, power grid, and clock tree design).
• Understanding of DFT including Scan, MBIST and LBIST. Understanding of performance, power and area (PPA) trade-offs.

About the job
In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems.
As a Physical Design Engineer, you will collaborate closely with cross-functional design, Design for Testing (DFT), architecture, power, and packaging engineers. In this role, you will address complex physical implementation issues at advanced process nodes, utilizing micro-architectural insights and practical logic circuit solutions. You will evaluate and optimize design options to deliver Performance, Power, and Area (PPA) for the next generation of Tensor Processing Unit (TPU) blocks and sub-chips.
The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.
We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.
Individual pay is determined by factors including job-related skills, experience, and relevant education or training.
US: $138000 - $198000 (USD) 15% bonus target equity benefits
Learn more about benefits at Google .
Responsibilities

• Perform physical design of complex blocks from Register-Transfer Level (RTL) to Graphic Data System (GDS).
• Use problem-solving, debugging skills and collaborate cross-functional teams to achieve the best Power/Performance Analysis (PPA).
• Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized implementation and sign-off domains.
• Work with architects and logic designers to drive architectural feasibility studies, develop timing, power and area design goals, and explore RTL/design trade-offs for physical design closure.

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