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Google Hardware Verification Engineer Jobs (NOW HIRING)

Talencore

Sr. RTL Verification Engineer

Redwood City, CA · On-site

$166K - $203K/yr

We are seeking a Sr. RTL Verification Engineer to join our team in Redwood City to bring the power ... Collaborate with experts in hardware, software, and machine learning to develop advanced computing ...

Purple Hires Inc

Design Verification Engineer

Plano, TX · On-site

$130K - $158K/yr

and other details - We are seeking an ASIC Design Verification Engineer whose role will be to ... Solid understanding of SystemVerilog, digital logic, and hardware verification flows. Proficiency ...

InterSources Inc.

Verification Engineer

Saratoga, CA · On-site

$150K/yr

Qualifications * ME/BE in Electrical Engineering, Computer Engineering, or related field ... Expertise in Hardware Verification and Hardware Verification Methodology (e.g., System Verilog, OVM ...

Apple

CPU Design Verification Engineer

Austin, TX

$134K - $164K/yr

The people who work here have reinvented entire industries with all Apple Hardware products. The ... Description As a CPU Design Verification Engineer owning the verification of a certain area of ...

Apple

CPU Design Verification Engineer

Cambridge, MA · On-site

$148K - $181K/yr

The people who work here have reinvented entire industries with all Apple Hardware products. The ... Description As a CPU Design Verification Engineer owning the verification of a certain area of ...

Apple

CPU Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

The people who work here have reinvented entire industries with all Apple Hardware products. The ... Description As a CPU Design Verification Engineer owning the verification of a certain area of ...

Apple

CPU Design Verification Engineer

Austin, TX

$134K - $164K/yr

The people who work here have reinvented entire industries with all Apple Hardware products. The ... Description As a CPU Design Verification Engineer owning the verification of a certain area of ...

Apple

CPU Design Verification Engineer

Austin, TX · On-site

$134K - $164K/yr

The people who work here have reinvented entire industries with all Apple Hardware products. The ... Description As a CPU Design Verification Engineer owning the verification of a certain area of ...

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Google Hardware Verification Engineer information

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$51K

$146.2K

$196.5K

How much do google hardware verification engineer jobs pay per year?

As of Sep 10, 2026, the average yearly pay for google hardware verification engineer in the United States is $146,230.00, according to ZipRecruiter salary data. Most workers in this role earn between $123,500.00 and $163,000.00 per year, depending on experience, location, and employer.

What are popular job titles related to Google Hardware Verification Engineer jobs?

For Google Hardware Verification Engineer jobs, the most frequently searched job titles are:

Infographic showing various Google Hardware Verification Engineer job openings in the United States as of August 2026, with employment types broken down into 92% Full Time, 2% Part Time, and 6% Contract. Highlights an 87% Physical, 4% Hybrid, and 9% Remote job distribution, with an average salary of $146,230 per year, or $70.3 per hour.

Design Verification Engineer - Remote - Contract opportunity

Irvine, CA • Remote

Zodiac Solutions
Library and Information Services • 11 - 50 employees
Learn more about Zodiac Solutionsexternal

$139K - $169K/yr

Contractor

Re-posted 19 days ago

Job description

Role – Design Verification Engineer

Location – Remote (must be aligned with PST time zone)

Duration- Contract opportunity

 Job Description and other details –

We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon. 

Qualifications 

  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
  • 3+ years of experience in ASIC/SoC verification.
  • Solid understanding of SystemVerilog, digital logic, and hardware verification flows.
  • Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision) and coverage tool.
  • Experience with test planning, testbench development, constrained-random testing, and coverage analysis.
  • Familiarity with a scripting language (ex: Python, Perl, TCL) and revision control system (ex: Git). 

Responsibilities 

  • Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
  • Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
  • Write SystemVerilog Assertions (SVA) and integrate formal verification where appropriate.
  • Drive constrained-random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
  • Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
  • Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
  • Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
  • Participate in design reviews and microarchitecture discussions.