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Functional Verification Application Engineer Jobs

Coordinate cross functional efforts with Design, SW, Architecture team to achieve full coverage ... Using system full application to verify performance and identify short falls. Key Responsibilities:

Coordinate cross functional efforts with Design, SW, Architecture team to achieve full coverage ... Using system full application to verify performance and identify short falls. Key Responsibilities

Design Verification Engineer

San Jose, CA · On-site

$159K - $194K/yr

Design Verification Engineer Location: San Jose, CA - Onsite Experience: 8+ years Mandatory Skills ... · Perform functional verification of RTL designs · Debug RTL and testbench issues · Drive ...

New

Application Engineer

Plymouth, MI · On-site

$36 - $38/hr

Perform calibration, verification, and validation of brake systems, including electronic brake ... Effective communication and collaboration skills for cross-functional project coordination. Work ...

Formal Verification Engineer

San Diego, CA · On-site

$144K/yr

... functional verification EDA tools: VCS, IUS, ModelSim, Jasper, 0-in, IFV, OneSpin, SLEC, etc is ... Unix/Linux shell programming, Perl, Java, Makefile, XML, XML DOM, XPath, XSLT, revision management ...

Verification Engineer

Santa Clara, CA · On-site

$158K/yr

Santa Clara, CA & Contract § Participate in the functional verification of a block(s) of complex ASICs and/or IP cores for a combined CPU/GPU development effort. § Be part of a team of design and ...

Verification Engineer

Santa Clara, CA · On-site

$160K/yr

... in need of Verification Engineers. Lets talk about what you want next! ASIC Verification ... You'll also support gate level functional verification, run regressions, handle bug tracking ...

Verification Engineer

Santa Clara, CA · On-site

$160K/yr

... in need of Verification Engineers. Lets talk about what you want next! ASIC Verification ... You'll also support gate level functional verification, run regressions, handle bug tracking ...

Verification Engineer (Remote)

Campbell, CA · On-site

$157K/yr

Staff Verification Engineer Office Located in Campbell, CA ( 100 % remote considered) Duration ... Expertise in functional coverage flows, property checking and Assertions. Prior experience with VIP ...

Showing results 21-40

Functional Verification Application Engineer information

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$50.5K

$110.7K

$152K

How much do functional verification application engineer jobs pay per year?

As of Sep 11, 2026, the average yearly pay for functional verification application engineer in the United States is $110,698.00, according to ZipRecruiter salary data. Most workers in this role earn between $84,000.00 and $135,000.00 per year, depending on experience, location, and employer.

What are popular job titles related to Functional Verification Application Engineer jobs?

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Infographic showing various Functional Verification Application Engineer job openings in the United States as of June 2026, with employment types broken down into 65% Full Time, 34% Part Time, and 1% Contract. Highlights an 88% Physical, 4% Hybrid, and 8% Remote job distribution, with an average salary of $110,698 per year, or $53.2 per hour.

EICDV5235 Design Verification Engineer Onsite

San Jose, CA • On-site

$159K - $194K/yr

Full-time

Re-posted 13 days ago


Job description

Overview:
Job Title: Design Verification Engineer EICDV5235
Location: San Jose ,CA , Onsite
Duration: Full Time
12+ years of experience in SOC/IP/block level functional verification using System Verilog/UVM.
• Must have executed at-least 1 to 2 SoC/IP Verification projects on C++ based verification environment
• Knowledge of Ethernet PCS layer, and or OTN G709 is required.
• Strong knowledge of C++ • UVM and System Verilog added advantage.
• Must have worked on development of test plan, testbench components, verification environment, interface agents, Scoreboards.
• Understanding of complete functional verification cycle will be added advantage
• Skills to debug RTL & testbench issues, test failures. • Experience on verification closure by closing Coverage and bug reports
• Understanding of customer dynamic environment change and adopt run time changes in schedule, design etc.
Qualifications:
• B.E., B.TECH, M.E. M. TECH
Skills:
UVM,SOC,Verilog,ASIC