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Functional Verification Application Engineer Jobs

Jobtailor

Mixed Signal Design Verification Engineer

Oregon, WI · On-site

$133K - $163K/yr

* Perform functional verification of mixed signal logic components, including analog behavioral ... Collaborate with digital and analog architects, RTL developers, and physical design teams * Improve ...

Intel Corporation

Physical Verification Engineer

Phoenix, AZ · On-site

$135K/yr

... Verification Application Engineer provides specialized technical support to Intel Foundry Services ... Create application notes, comprehensive documentation, and deliver technical training presentations ...

Intel

Physical Verification Engineer

Hillsboro, OR · On-site

$148K/yr

... Verification Application Engineer provides specialized technical support to Intel Foundry Services ... Create application notes, comprehensive documentation, and deliver technical training presentations ...

Intel

Physical Verification Engineer

Phoenix, AZ · On-site

$135K/yr

... Verification Application Engineer provides specialized technical support to Intel Foundry Services ... Create application notes, comprehensive documentation, and deliver technical training presentations ...

Socket.dev

CPU Verification Engineer

Fort Collins, CO · On-site

$134K/yr

Perform functional verification of L2 and L3 cache subsystems at block and full-chip levels ... Strong C++ programming skills with experience building verification infrastructure. * Solid ...

Intel

Physical Verification Engineer

Santa Clara, CA

$159K/yr

... Verification Application Engineer provides specialized technical support to Intel Foundry Services ... Create application notes, comprehensive documentation, and deliver technical training presentations ...

Weekday AI

ASIC/SoC Design & Verification Engineer

$70 - $100/hr

Hands-on experience in ASIC and/or SoC design , functional verification, or digital hardware ... Reasonable accommodations are available throughout the application and engagement process. Contract ...

Embtel Inc

Senior Verification Engineer (Remote)

Campbell, CA · On-site

$157K/yr

Senior Verification Engineer Location: Campbell, CA ( 100 % remote considered) Duration: Full Time ... Develop/write testbench, develop/write tests, develop/write Functional Coverage, Assertions, Covers ...

Lorven Technologies

Design verification Engineer

San Jose, CA · On-site

$158K - $192K/yr

Job Title: Design Verification Engineer Location: San Jose, CA We are seeking DV engineers to ... Perform functional verification of RTL designs * Debug RTL and testbench issues * Drive coverage ...

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Functional Verification Application Engineer information

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$50.5K

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$152K

How much do functional verification application engineer jobs pay per year?

As of Sep 11, 2026, the average yearly pay for functional verification application engineer in the United States is $110,698.00, according to ZipRecruiter salary data. Most workers in this role earn between $84,000.00 and $135,000.00 per year, depending on experience, location, and employer.

What are popular job titles related to Functional Verification Application Engineer jobs?

For Functional Verification Application Engineer jobs, the most frequently searched job titles are:

Infographic showing various Functional Verification Application Engineer job openings in the United States as of June 2026, with employment types broken down into 65% Full Time, 34% Part Time, and 1% Contract. Highlights an 88% Physical, 4% Hybrid, and 8% Remote job distribution, with an average salary of $110,698 per year, or $53.2 per hour.

Applied ML - Functional Verification Engineer

San Jose, CA • On-site

Cadence Design Systems, Inc.
Software Development • 5 - 10K employees
Learn more about Cadence Design Systems, Inc.external

$154K - $286K/yr

Full-time

Medical, Dental, Vision, Retirement, PTO

Re-posted 9 days ago

Cadence Design Systems rating

9.0

Company rating: 9.0 out of 10

Based on 5 frontline employees who took The Breakroom Quiz

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world's most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health. At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.
Position Overview
We are seeking a results driven Pre-Silicon Verification Engineer with extensive experience in function verification (formal verification and/or simulation/UVM verification) and a passion for leveraging artificial intelligence to redefine the verification landscape. In this role, you will operate at the forefront of semiconductor design and AI innovation, utilizing advanced AI tools to architect, design, and validate the next generation of verification methodologies. You will collaborate closely with a highly skilled team of machine learning engineers experienced in training large language models at scale, as well as accomplished software engineers with proven expertise in product development and deployment. This person will to be part of the ChipStack AI Super Agent team in San Jose, CA - working on the world's first agentic AI platform that autonomously designs and verifies chips with up to 10× productivity gains. Cadence has been nominated as a Great Place to Work globally and in Brazil, and is also a Fortune 100 Best Companies to Work For.
Key Responsibilities
  • Contribute to the application of machine learning techniques aimed at streamlining traditional pre-silicon functional verification methodologies like formal verification and UVM.
  • Develop agentic AI solutions using LLMs and latest ML technologies to accelerate pre-silicon Design Verification process.
  • Employ AI enhanced Electronic Design Automation (EDA) tools to improve and expedite both the design and verification lifecycles.
  • Engage directly with customers to understand requirements and deliver innovative, practical verification strategies.
  • Collaborate effectively with machine learning and software engineering teams to validate output correctness, efficiency, and quality.
  • Maintain current knowledge of advancements in AI-powered hardware verification and actively participate in fostering internal knowledge growth.

Required Qualifications
  • BS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience
  • Proven expertise of more than 3 years in at least one of the pre-silicon ASIC verification methodologies such as Formal, SV/UVM and/or OVM.
  • Advanced skills in debugging pre-silicon verification failures using waveform viewers and simulation analysis tools.
  • Hands-on experience with industry standard EDA tools (e.g., Jasper, Xcelium, IMC).
  • Strong programming skills in Verilog, System Verilog and Python
  • Excellent communication skills and the ability to thrive in a team-oriented environment.
  • Self-motivated, with a proactive approach to problem solving, continuous learning, and innovation.
  • Exposure to LLMs and ML technologies like RAG, RFT, RL, and Agentic frameworks would be a plus.

The Cadence Advantage
  • The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.
  • Cadence's employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.
  • The unique "One Cadence - One Team" culture promotes collaboration within and across teams to ensure customer success
  • Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests
  • You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other-every day.

The annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
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