Design Verification Engineer
$134K - $164K/yr
We have an opportunity for an outstandingly hardworking design verification engineer. As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming ...
Design Verification Engineer
$134K - $164K/yr
We have an opportunity for an outstandingly hardworking design verification engineer. As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming ...
Design Verification Engineer
Austin, TX · On-site
$134K - $164K/yr
We have an opportunity for an outstandingly hardworking design verification engineer. As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming ...
Design Verification Engineer
Austin, TX · On-site
$134K - $164K/yr
We have an opportunity for an outstandingly hardworking design verification engineer. As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming ...
Design Verification Engineer
Los Angeles, CA · On-site
$146K - $178K/yr
We have an opportunity for an outstandingly hardworking design verification engineer. As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming ...
Design Verification Engineer
Los Angeles, CA · On-site
$146K - $178K/yr
We have an opportunity for an outstandingly hardworking design verification engineer. As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming ...
Design Verification Engineer
Cupertino, CA · On-site
$167K - $204K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology organization ...
Design Verification Engineer
Cupertino, CA · On-site
$167K - $204K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology organization ...
Design Verification Engineer
San Diego, CA · On-site
$144K - $176K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love ...
Design Verification Engineer
San Diego, CA · On-site
$144K - $176K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love ...
GPU Design Verification Engineer
Santa Clara, CA · On-site
$159K - $195K/yr
The GPU Design Verification Engineer will be responsible for the pre-silicon RTL verification of sub-units in the Apple GPU. This includes deep understanding of the micro-architectural details of ...
GPU Design Verification Engineer
Santa Clara, CA · On-site
$159K - $195K/yr
The GPU Design Verification Engineer will be responsible for the pre-silicon RTL verification of sub-units in the Apple GPU. This includes deep understanding of the micro-architectural details of ...
Design Verification Engineer
Waltham, MA · On-site
$146K - $179K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology organization ...
Design Verification Engineer
Waltham, MA · On-site
$146K - $179K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology organization ...
Design Verification Engineer
$141K - $172K/yr
We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming ...
Design Verification Engineer
$141K - $172K/yr
We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love ...
Design Verification Engineer
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love ...
Design Verification Engineer
$141K - $172K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming ...
Design Verification Engineer
Beaverton, OR · On-site
$141K - $172K/yr
We have an opportunity for an outstandingly hardworking design verification engineer! As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming ...
Design Verification Engineer (San Jose)
San Jose, CA · On-site
$156K - $160K/yr
Design Verification Engineer Job Duration: 40 Hours / Week, Permanent position, Full time J ob Duties: Collaborate with design and development teams to understand product requirements and ...
Design Verification Engineer (San Jose)
San Jose, CA · On-site
$156K - $160K/yr
Design Verification Engineer Job Duration: 40 Hours / Week, Permanent position, Full time J ob Duties: Collaborate with design and development teams to understand product requirements and ...
Interface Design Verification Engineer
San Jose, CA · On-site
$159K - $194K/yr
Interface Design Verification Engineer Location: San Jose, CA Looking for engineers with strong protocol expertise to verify industry-standard interface IPs such as PCIe, DDR, Ethernet, USB, etc. Key ...
Interface Design Verification Engineer
San Jose, CA · On-site
$159K - $194K/yr
Interface Design Verification Engineer Location: San Jose, CA Looking for engineers with strong protocol expertise to verify industry-standard interface IPs such as PCIe, DDR, Ethernet, USB, etc. Key ...
Design Verification Engineer
$150K - $277K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology organization ...
Design Verification Engineer
$150K - $277K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology organization ...
Design Verification Engineer
$142K - $263K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love ...
Design Verification Engineer
$142K - $263K/yr
Design Verification Engineers at Apple are responsible for verifying the functionality and performance of Apple's premier SOCs. This is a critical job within Apple's Hardware Technology and we'd love ...
Senior Design Verification Engineer
San Diego, CA · On-site
$145K - $178K/yr
We are seeking a skilled Design Verification Engineer with strong expertise in System Verilog (SV) and UVM methodologies to join our team. The ideal candidate will have hands-on experience in ...
Senior Design Verification Engineer
San Diego, CA · On-site
$145K - $178K/yr
We are seeking a skilled Design Verification Engineer with strong expertise in System Verilog (SV) and UVM methodologies to join our team. The ideal candidate will have hands-on experience in ...
Senior Design Verification Engineer
Austin, TX · On-site
$134K - $164K/yr
Senior Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position along with long term stability and benefits? Correct Designs can give it all to you.
Senior Design Verification Engineer
Austin, TX · On-site
$134K - $164K/yr
Senior Design Verification Engineer Looking for new challenges? Would you like the variety of a contract position along with long term stability and benefits? Correct Designs can give it all to you.
Silicon Design Verification Engineer
San Jose, CA · On-site
$103K/yr
This is an exciting opportunity to work in the AMD SOC Verification Team as Silicon Design Verification Engineer where you will work with a team and experts in verification. THE PERSON: The candidate ...
Silicon Design Verification Engineer
San Jose, CA · On-site
$103K/yr
This is an exciting opportunity to work in the AMD SOC Verification Team as Silicon Design Verification Engineer where you will work with a team and experts in verification. THE PERSON: The candidate ...
Design Verification Engineer
Boise, ID · On-site
$129K - $158K/yr
Job Summary As a Design Verification Engineer at Micron Technology, Inc., you'll play a central role in validating complex memory architectures, ensuring speed, reliability, and innovation come ...
Design Verification Engineer
Boise, ID · On-site
$129K - $158K/yr
Job Summary As a Design Verification Engineer at Micron Technology, Inc., you'll play a central role in validating complex memory architectures, ensuring speed, reliability, and innovation come ...
SoC Design Verification Engineer
San Jose, CA · On-site
$158K - $192K/yr
SoC Design Verification Engineer Location: San Jose, CA We are looking for a highly skilled SoC/Performance DV engineer to drive system-level validation and performance characterization of complex ...
SoC Design Verification Engineer
San Jose, CA · On-site
$158K - $192K/yr
SoC Design Verification Engineer Location: San Jose, CA We are looking for a highly skilled SoC/Performance DV engineer to drive system-level validation and performance characterization of complex ...
Freelance Entry Level Design Verification Engineer information
See salary details
$30K - $38K
2% of jobs
$38K - $46K
10% of jobs
$51.3K is the 25th percentile. Wages below this are outliers.
$46K - $54K
20% of jobs
$54K - $62K
13% of jobs
The median wage is $64K / yr.
$62K - $70K
21% of jobs
$75.2K is the 75th percentile. Wages above this are outliers.
$70K - $78K
14% of jobs
$78K - $86K
7% of jobs
$86K - $94K
5% of jobs
$94K - $102K
3% of jobs
$102K - $110K
2% of jobs
$110K - $118K
2% of jobs
$30K
$69.4K
$118K
How much do freelance entry level design verification engineer jobs pay per year?
As of Jul 8, 2026, the average yearly pay for freelance entry level design verification engineer in the United States is $69,362.00, according to ZipRecruiter salary data. Most workers in this role earn between $51,500.00 and $78,500.00 per year, depending on experience, location, and employer.
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Apple rating
8.1
Based on 667 frontline employees who took The Breakroom Quiz
5th of 30 rated technology retailers
Job description
At Apple, we work to craft products that enrich people’s lives. Do you love working on challenges that no one has solved yet and changing the game? We have an opportunity for an outstandingly hardworking design verification engineer. As a member of our wide-ranging group, you will have the rare and extraordinary opportunity to craft upcoming products that will delight and encourage millions of Apple’s customers every single day.
This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
Description
In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage.
Furthermore, you will learn to develop verification plans for all features under your care, execute verification plans, including design bring-up, DV environment bring- up, regression enabling all features under your care, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage.","responsibilities":"Study design specification and create test plan
Develop infrastructure in SystemVerilog/UVM to stress the design
Develop and fix failures from regressions, close bugs
Use LLMs to do verification efficiently
Preferred Qualifications
BS degree in technical subject area and a minimum 3 years relevant industry experience or equivalent strongly preferred
Deep knowledge of SystemVerilog and UVM
Deep knowledge in developing scalable and portable test-benches
Proven experience with verification methodologies and tools such as simulators, waveform viewers
Build and run automation, coverage collection, gate level simulations
Some UVM knowledge, C/C++ level knowledge
Deep experience with serial protocols such as PCIe or USB, parallel protocol such as DDR
Basic knowledge of formal verification methodology
Some experience with power-aware (UPF) or similar verification methodology
Knowledge of one of the scripting languages such as Python, Perl, TCL
Some working experience using LLMs for efficiency and quality
Minimum Qualifications
Minimum requirement of a bachelors degree
This role is for a DV engineer who will enable us to produce fully functional first silicon for IP designs. The responsibilities include all phases of pre-silicon verification including but not limited to: establishing DV methodology, test-plan development, verification environment development including stimulus and checkers, test-writing, debug, coverage, sign-off for RTL freeze and tape-out.
Description
In this role, you will be responsible for ensuring bug-free first silicon for part of the SoC / IP and are encouraged to develop detailed test and coverage plans based on the micro-architecture You are responsible for developing verification methodology suitable for the IP, ensuring a scalable and portable environment. You will get to develop verification environment, including all the respective components such as stimulus, checkers, assertions, trackers, coverage.
Furthermore, you will learn to develop verification plans for all features under your care, execute verification plans, including design bring-up, DV environment bring- up, regression enabling all features under your care, and debug of the test failures. You will also learn to develop block, IP and SoC level test-benches track and report DV progress using a variety of metrics, including bugs and coverage.","responsibilities":"Study design specification and create test plan
Develop infrastructure in SystemVerilog/UVM to stress the design
Develop and fix failures from regressions, close bugs
Use LLMs to do verification efficiently
Preferred Qualifications
BS degree in technical subject area and a minimum 3 years relevant industry experience or equivalent strongly preferred
Deep knowledge of SystemVerilog and UVM
Deep knowledge in developing scalable and portable test-benches
Proven experience with verification methodologies and tools such as simulators, waveform viewers
Build and run automation, coverage collection, gate level simulations
Some UVM knowledge, C/C++ level knowledge
Deep experience with serial protocols such as PCIe or USB, parallel protocol such as DDR
Basic knowledge of formal verification methodology
Some experience with power-aware (UPF) or similar verification methodology
Knowledge of one of the scripting languages such as Python, Perl, TCL
Some working experience using LLMs for efficiency and quality
Minimum Qualifications
Minimum requirement of a bachelors degree
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976