Freelance Asic Rtl Design Engineer Jobs in Stanton, CA

THE OPPORTUNITY Silvus is seeking a Principal FPGA / RTL Design Engineer who will report to the ... Experience with wireless communication systems on FPGA or ASIC designs. WORKING CONDITIONS AND ...

Work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation ... Engineering, or related field. * 10+ years of experience in ASIC/SoC verification. * Solid ...

... Lead ASIC DFT Engineer to architect, implement, verify, and debug advanced DFT solutions for ... Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ...

THE OPPORTUNITY Silvus is seeking a Senior FPGA/RTL Design Engineer who will report to the Director ... Experience with communication systems on FPGA or ASIC designs. WORKING CONDITIONS & PHYSICAL ...

SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... RTL/design tradeoffs * Resolve design/timing/congestion and flow issues, identify potential ...

Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level ... Principal ASIC Design Engineer: $200,000.00 - $285,000.00/per year Your actual level and base ...

You will own the full physical design flow--from RTL handoff to GDSII--and collaborate closely with ... Engineering, or related field. * 10+ years of experience in ASIC physical design for high ...

... SR. SOC/ASIC PHYSICAL DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our ... RTL/design tradeoffs * Resolve design/timing/congestion and flow issues, identify potential ...

SR. ASIC DESIGN ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch ... Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level ...

Title - Lead ASIC DFT Engineer Location - Remote (must be aligned with PST time zone) Duration ... Collaborate with RTL design, verification, physical design, STA, and silicon validation teams to ...

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design group ...

Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level ... Principal ASIC Design Engineer: $200,000.00 - $285,000.00/per year Your actual level and base ...

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design group ...

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design group ...

As an ASIC Design Engineer on the Starshield team, you will be working on advanced development ... Define micro-architecture, implement the RTL in Verilog/System Verilog, integrate that in top level ...

... RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. Description In this highly visible role, you will be at the center of a silicon design group ...

THE OPPORTUNITY Silvus is seeking a Senior FPGA/RTL Design Engineer who will report to the Director ... Experience with communication systems on FPGA or ASIC designs. WORKING CONDITIONS & PHYSICAL ...

Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project ... Familiarity with LLM-assisted RTL or HDL generation tools (e.g., Copilot for hardware, or general ...

Lead and mentor a small team of FPGA/ASIC design engineers, including resource planning, project ... Familiarity with LLM-assisted RTL or HDL generation tools (e.g., Copilot for hardware, or general ...

Strong fundamentals in digital ASIC design, micro-architecture, and best RTL coding methods. * Firmware / embedded C development, including bare-metal programming on an on-chip RISC CPU IP (e.g ...