Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Verification: Engage with simulation-based and formal verification teams to ensure robust design ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Verification: Engage with simulation-based and formal verification teams to ensure robust design ...
RTL Design Engineer
Beaverton, OR · On-site
You will work with a variety of flows fundamental to modern silicon engineering: modeling and ... Python) Formal verification and low-power design methodologies Hardware-software co-design and ...
RTL Design Engineer
Beaverton, OR · On-site
You will work with a variety of flows fundamental to modern silicon engineering: modeling and ... Python) Formal verification and low-power design methodologies Hardware-software co-design and ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Verification: Engage with simulation-based and formal verification teams to ensure robust design ...
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Verification: Engage with simulation-based and formal verification teams to ensure robust design ...
RTL Design Engineer
Beaverton, OR · On-site
You will work with a variety of flows fundamental to modern silicon engineering: modeling and ... Python) Formal verification and low-power design methodologies Hardware-software co-design and ...
RTL Design Engineer
Beaverton, OR · On-site
You will work with a variety of flows fundamental to modern silicon engineering: modeling and ... Python) Formal verification and low-power design methodologies Hardware-software co-design and ...
RTL Design Engineer
$141K/yr
... Python) Formal verification and low-power design methodologies Hardware-software co-design and ... Engineering.
RTL Design Engineer
$141K/yr
... Python) Formal verification and low-power design methodologies Hardware-software co-design and ... Engineering.
RTL Design Engineer
Beaverton, OR · On-site
$141K/yr
You will work with a variety of flows fundamental to modern silicon engineering: modeling and ... Python) Formal verification and low-power design methodologies Hardware-software co-design and ...
RTL Design Engineer
Beaverton, OR · On-site
$141K/yr
You will work with a variety of flows fundamental to modern silicon engineering: modeling and ... Python) Formal verification and low-power design methodologies Hardware-software co-design and ...
ASIC Design and Integration Engineer
$129K - $194K/yr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Verification: Engage with simulation-based and formal verification teams to ensure robust design ...
ASIC Design and Integration Engineer
$129K - $194K/yr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Verification: Engage with simulation-based and formal verification teams to ensure robust design ...
ASIC Design and Integration Engineer
$150K - $277K/yr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Verification: Engage with simulation-based and formal verification teams to ensure robust design ...
ASIC Design and Integration Engineer
$150K - $277K/yr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Verification: Engage with simulation-based and formal verification teams to ensure robust design ...
ASIC Design and Integration Engineer
$129K - $194K/yr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Verification: Engage with simulation-based and formal verification teams to ensure robust design ...
ASIC Design and Integration Engineer
$129K - $194K/yr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Verification: Engage with simulation-based and formal verification teams to ensure robust design ...
ASIC Design and Integration Engineer
$150K - $277K/yr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Verification: Engage with simulation-based and formal verification teams to ensure robust design ...
ASIC Design and Integration Engineer
$150K - $277K/yr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Verification: Engage with simulation-based and formal verification teams to ensure robust design ...
ASIC Design and Integration Engineer
$184K - $324K/yr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Verification: Engage with simulation-based and formal verification teams to ensure robust design ...
ASIC Design and Integration Engineer
$184K - $324K/yr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Verification: Engage with simulation-based and formal verification teams to ensure robust design ...
ASIC Design and Integration Engineer
$184K - $324K/yr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Verification: Engage with simulation-based and formal verification teams to ensure robust design ...
ASIC Design and Integration Engineer
$184K - $324K/yr
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer ... Verification: Engage with simulation-based and formal verification teams to ensure robust design ...
Senior Engineer, Digital Design Engineering
Beaverton, OR · On-site
$121K - $174K/yr
Apply formal design and verification techniques to design and architect detailed verification plans ... Engineer or related occupation performing digital or mixed signal design and verification. Must ...
Senior Engineer, Digital Design Engineering
Beaverton, OR · On-site
$121K - $174K/yr
Apply formal design and verification techniques to design and architect detailed verification plans ... Engineer or related occupation performing digital or mixed signal design and verification. Must ...
Senior Engineer, Digital Design Engineering
$121K - $174K/yr
Apply formal design and verification techniques to design and architect detailed verification plans ... Engineer or related occupation performing digital or mixed signal design and verification. Must ...
Senior Engineer, Digital Design Engineering
$121K - $174K/yr
Apply formal design and verification techniques to design and architect detailed verification plans ... Engineer or related occupation performing digital or mixed signal design and verification. Must ...
FPGA/RTL Design Engineer - III (W2 Only)
Hillsboro, OR · On-site
$134K - $184K/yr
FPGA/RTL Design Engineer - III Location: Hillsboro, OR Duration: 4 + Months This is a senior RTL ... and formal verification tools Experience in synthesis and development of timing constraints ...
FPGA/RTL Design Engineer - III (W2 Only)
Hillsboro, OR · On-site
$134K - $184K/yr
FPGA/RTL Design Engineer - III Location: Hillsboro, OR Duration: 4 + Months This is a senior RTL ... and formal verification tools Experience in synthesis and development of timing constraints ...
Use formal tools and static checkers to guarantee RTL quality. You will also support design ... verification to insure bug-free first silicon. Responsibilities will include driving functional and ...
Use formal tools and static checkers to guarantee RTL quality. You will also support design ... verification to insure bug-free first silicon. Responsibilities will include driving functional and ...
DDR Design Engineer
Beaverton, OR · On-site
Use formal tools and static checkers to guarantee RTL quality. You will also support design ... verification to insure bug-free first silicon. Responsibilities will include driving functional and ...
DDR Design Engineer
Beaverton, OR · On-site
Use formal tools and static checkers to guarantee RTL quality. You will also support design ... verification to insure bug-free first silicon. Responsibilities will include driving functional and ...
DDR Design Engineer
Beaverton, OR · On-site
Use formal tools and static checkers to guarantee RTL quality. You will also support design ... verification to insure bug-free first silicon. Responsibilities will include driving functional and ...
DDR Design Engineer
Beaverton, OR · On-site
Use formal tools and static checkers to guarantee RTL quality. You will also support design ... verification to insure bug-free first silicon. Responsibilities will include driving functional and ...
Use formal tools and static checkers to guarantee RTL quality. You will also support design ... verification to insure bug-free first silicon. Responsibilities will include driving functional and ...
Use formal tools and static checkers to guarantee RTL quality. You will also support design ... verification to insure bug-free first silicon. Responsibilities will include driving functional and ...
ASIC Physical Design Principal Consultant
Hillsboro, OR · On-site
$148K - $152K/yr
At least 9 years of experience in Netlist-GDS flow with Synthesis, Layout (Floorplan, Place and Route, clock tree synthesis), Static Timing Analysis, Formal Verification, Physical Verification(DRC ...
ASIC Physical Design Principal Consultant
Hillsboro, OR · On-site
$148K - $152K/yr
At least 9 years of experience in Netlist-GDS flow with Synthesis, Layout (Floorplan, Place and Route, clock tree synthesis), Static Timing Analysis, Formal Verification, Physical Verification(DRC ...
Formal Verification Engineer information
See Portland, OR salary details
$84.8K - $96.7K
1% of jobs
$96.7K - $108.7K
1% of jobs
$108.7K - $120.6K
1% of jobs
$120.6K - $132.5K
1% of jobs
$139.5K is the 25th percentile. Wages below this are outliers.
$132.5K - $144.4K
35% of jobs
The median wage is $146.7K / yr.
$144.4K - $156.3K
54% of jobs
$156.3K - $168.2K
1% of jobs
$168.2K - $180.1K
1% of jobs
$180.1K - $192K
2% of jobs
$192K - $203.9K
1% of jobs
$203.9K - $215.8K
1% of jobs
$84.8K
$151.2K
$215.8K
How much do formal verification engineer jobs pay per year?
As of Aug 22, 2026, the average yearly pay for formal verification engineer in Portland, OR is $151,249.00, according to ZipRecruiter salary data. Most workers in this role earn between $144,200.00 and $144,200.00 per year, depending on experience, location, and employer.
What is a formal verification engineer?
A Formal Verification Engineer is responsible for ensuring the correctness of hardware or software designs using mathematical and logical techniques. They apply formal methods to verify that a system behaves as intended, identifying potential design flaws early in the development process. This involves writing formal properties, using model checking tools, and collaborating with design and validation teams. Their work helps improve reliability, reduce bugs, and enhance the efficiency of verification compared to traditional simulation-based methods.
What are the common daily responsibilities of a formal verification engineer?
As a Formal Verification Engineer, your typical day involves creating and analyzing formal properties, developing assertions, and using formal verification tools to mathematically prove correctness of hardware designs. You'll collaborate closely with design and simulation teams to review specifications, identify verification requirements, and debug issues found during the verification process. Regular documentation of findings, participation in code and design reviews, and ongoing learning about new verification methodologies are also important parts of the role. This dynamic environment requires both technical depth and proactive teamwork to ensure high-quality design outcomes.
What are the key skills and qualifications needed to thrive as a formal verification engineer?
To thrive as a Formal Verification Engineer, you need a strong background in digital design, computer architecture, and logic, typically supported by a degree in electrical engineering, computer science, or a related field. Expertise in formal verification tools such as Cadence JasperGold, Synopsys VC Formal, or Mentor Questa, along with proficiency in hardware description languages (HDLs) like Verilog or VHDL, is essential. Strong analytical thinking, attention to detail, and effective communication skills help you collaborate with design and verification teams and present complex findings. These competencies are critical for ensuring hardware systems are bug-free, reliable, and meet stringent industry standards.
What are the most commonly searched types of Formal Verification Engineer jobs in Portland, OR?
The most popular types of Formal Verification Engineer jobs in Portland, OR are:
What are popular job titles related to Formal Verification Engineer jobs in Portland, OR?
For Formal Verification Engineer jobs in Portland, OR, the most frequently searched job titles are:
What job categories do people searching Formal Verification Engineer jobs in Portland, OR look for?
The top searched job categories for Formal Verification Engineer jobs in Portland, OR are:
What cities near Portland, OR are hiring for Formal Verification Engineer jobs?
Cities near Portland, OR with the most Formal Verification Engineer job openings:
Apple rating
8.0
Based on 677 frontline employees who took The Breakroom Quiz
7th of 30 rated technology retailers
Job description
Apple's Silicon Engineering team is looking for a highly skilled and motivated ASIC Design Engineer to join our dynamic group. In this role, you will develop custom SoCs that drive the performance and efficiency of Apple's products. You will work on cutting-edge technologies and collaborate with cross-functional teams to deliver groundbreaking solutions.
Description
Design and Development: Design, implementation, and verification of complex ASICs. Develop RTL using SystemVerilog and perform synthesis.
Verification: Engage with simulation-based and formal verification teams to ensure robust design validation.
Integration and Testing: Collaborate with hardware and software teams to integrate digital designs into complex SoCs.
Timing and Power Analysis: Conduct timing analysis and power optimization to achieve PPA goals.
Documentation and Reporting: Create detailed micro-architecture and design documentation.
Minimum Qualifications
Minimum of BS + 3 years relevant industry experience
Preferred Qualifications
Educational Background: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
Experience: 3+ years of proven experience in ASIC design, including RTL design and verification. Hands-on experience with ASIC design tools and methodologies is essential.
Technical Skills: Proficiency in SystemVerilog, RTL design, synthesis, and timing analysis.
Problem-Solving: Strong analytical and problem-solving skills.
Collaboration: Excellent communication and teamwork skills, work effectively in cross-functional teams.
Attention to Detail: Meticulous attention to detail and a commitment to delivering high-quality designs.
Experience with high-speed I/O design and protocols. Knowledge of PCIe is a plus.
Familiarity with custom ASIC design and FPGA prototyping.
Hands on experience in all aspects of front-end chip development process (e.g., CDC/RDC, LINT, LEC, etc.).
Knowledge of low-power design techniques and power optimization strategies.
Description
Design and Development: Design, implementation, and verification of complex ASICs. Develop RTL using SystemVerilog and perform synthesis.
Verification: Engage with simulation-based and formal verification teams to ensure robust design validation.
Integration and Testing: Collaborate with hardware and software teams to integrate digital designs into complex SoCs.
Timing and Power Analysis: Conduct timing analysis and power optimization to achieve PPA goals.
Documentation and Reporting: Create detailed micro-architecture and design documentation.
Minimum Qualifications
Minimum of BS + 3 years relevant industry experience
Preferred Qualifications
Educational Background: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
Experience: 3+ years of proven experience in ASIC design, including RTL design and verification. Hands-on experience with ASIC design tools and methodologies is essential.
Technical Skills: Proficiency in SystemVerilog, RTL design, synthesis, and timing analysis.
Problem-Solving: Strong analytical and problem-solving skills.
Collaboration: Excellent communication and teamwork skills, work effectively in cross-functional teams.
Attention to Detail: Meticulous attention to detail and a commitment to delivering high-quality designs.
Experience with high-speed I/O design and protocols. Knowledge of PCIe is a plus.
Familiarity with custom ASIC design and FPGA prototyping.
Hands on experience in all aspects of front-end chip development process (e.g., CDC/RDC, LINT, LEC, etc.).
Knowledge of low-power design techniques and power optimization strategies.
About Apple
Sourced by ZipRecruiter
Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.
Industry
Computer and electronic product manufacturing
Company size
10,000+ Employees
Headquarters location
Cupertino, CA, US
Year founded
1976