Formal Verification Engineer Jobs in Florida (NOW HIRING)

FPGA Design Engineer

Job Description

We are seeking a FPGA Design Engineer with over 8 years of experience to develop architecture, implementation, and verification for complex, high-speed FPGA solutions. The ideal candidate will have expertise in high-bandwidth interfaces such as PCIe Gen4/5, 10 to 100G+ Ethernet, and DDR4/DDR5. Strong skills in RTL design (VHDL/Verilog/SystemVerilog), timing closure, and block design development are essential. This role involves driving FPGA design from concept through production, integrating vendor IP, optimizing for low latency and high throughput, and performing rigorous verification and lab validation. The engineer will be supporting the development of a cryptography platform and collaborate across hardware and software teams, mentor junior engineers, and ensure designs meet stringent reliability and compliance standards.

Responsibilities

• Lead full life-cycle FPGA development, from requirements and architecture through RTL implementation (Verilog/VHDL), verification, and system integration across multiple FPGA families.
• Define and document FPGA architecture, including block diagrams, clocking strategies, and trade-off analyses; participate in and conduct design reviews.
• Develop robust, reusable, and self-checking testbenches; implement functional coverage models and achieve code coverage closure.
• Create and execute detailed test plans, procedures, and reports; ensure verification rigor and traceability.
• Collaborate with hardware and software teams to integrate FPGA designs at the board and system level; support lab bring-up, debug, and qualification testing.
• Implement and validate JTAG boundary scan and other DFT features; ensure compliance with design-for-test and reliability standards.
• Drive continuous improvement in design practices, coding standards, and verification methodologies; mentor junior engineers and contribute to technical reviews.

Essential Skills

• 8+ years of experience to develop architecture, implementation, and verification for complex, high-speed FPGA solutions
• Strong proficiency in RTL design using Verilog/VHDL, including custom implementations beyond vendor IP integration.
• Strong experience in testbench development, functional coverage, and verification of complex FPGA designs.
• Proficient with FPGA simulation and synthesis tools (e.g., QuestaSim, Riviera-PRO, Xilinx Vivado, Intel Quartus).
• Proficiency in FPGA architecture and optimization techniques for timing closure, floor-planning, and resource utilization.
• Ability to perform FPGA power estimation and analysis using vendor tools and optimize designs for power and thermal constraints.
• Strong understanding of high-speed interfaces (PCIe, Ethernet, Serial RapidIO, DDRx) and control protocols (I²C, SPI, RS-232/422).
• Experience with System-on-Chip (SoC) technologies.
• Must have an Active DoD Secret Clearance

Additional Skills & Qualifications

• Proficiency in FPGA Block Design development and debugging (e.g., Vivado, Libero).
• Familiarity with Universal Verification Methodology (UVM).
• Familiarity with Microsemi Libero and Lattus Diamond.
• Familiarity with revision control systems (Git/Bitbucket) and scripting in Python, TCL, or Linux shell for automation.
• Skilled in FPGA lab validation using oscilloscopes, logic analyzers, and protocol analyzers.
• Support JTAG Boundary scan design and testing.
• Strong oral and written communication skills, with ability to document and present technical work clearly.
• Experience collaborating in Agile environments and using tools like Jira and requirements management systems (e.g., Jama).
• Understanding of formal verification processes and compliance standards.

Work Environment

This position requires 100% onsite work due to the nature of the projects. The company offers a stable work environment with a 9/80 schedule, allowing every other Friday off. The position can be Contract-to-Hire or just long term Contract (w2). Actalent offers benefits.

This is a Contract to Hire position based out of Melbourne, FL.

The pay range for this position is $75.00 - $90.00/hr.

Eligibility requirements apply to some benefits and may depend on your job classification and length of employment. Benefits are subject to change and may be subject to specific elections, plan, or program terms. If eligible, the benefits available for this temporary role may include the following: • Medical, dental & vision • Critical Illness, Accident, and Hospital • 401(k) Retirement Plan – Pre-tax and Roth post-tax contributions available • Life Insurance (Voluntary Life & AD&D for the employee and dependents) • Short and long-term disability • Health Spending Account (HSA) • Transportation benefits • Employee Assistance Program • Time Off/Leave (PTO, Vacation or Sick Leave)

This is a fully onsite position in Melbourne,FL.

This position is anticipated to close on Aug 11, 2026.

About Actalent

Actalent is a global leader in engineering and sciences services and talent solutions. We help visionary companies advance their engineering and science initiatives through access to specialized experts who drive scale, innovation and speed to market. With a network of almost 20,000 consultants and 5,000 clients across the U.S., Canada, Asia and Europe, Actalent serves many of the Fortune 500. We are proud to be an Engineering News-Record (ENR) Top 500 Design Firm for our engineering design services and a ClearlyRated Best of Staffing® winner for both client and talent service.

The company is an equal opportunity employer and will consider all applications without regard to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.

If you would like to request a reasonable accommodation, such as the modification or adjustment of the job application process or interviewing process due to a disability, please email actalentaccommodation@actalentservices.com for other accommodation options.

San Francisco Fair Chance Ordinance: Pursuant to the San Francisco Fair Chance Ordinance, for all positions located in the city and county of San Francisco, we will consider for employment qualified applicants with arrest and conviction records.

Massachusetts Lie Detector: It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.

Use of Artificial Intelligence (AI): We may use Artificial Intelligence (AI) to support parts of our hiring process, including sourcing, screening, and evaluating candidates. AI helps assess applications and qualifications, but final decisions are made by our hiring team. By applying, you acknowledge and agree that your application may be reviewed using AI tools.