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Formal Verification Engineer Jobs in Florida (NOW HIRING)

AERONIX INC

Senior FPGA Design Engineer

Melbourne, FL · On-site

$145K - $175K/yr

Understanding of formal verification processes and compliance standards. QUALIFICATIONS * Bachelor's Degree in Electrical Engineering, Computer Engineering, or related field. * Minimum 10 years of ...

AERONIX INC

Embedded Software Engineer

Melbourne, FL · On-site

$90K - $125K/yr

Embedded Software Engineer - Job Title: Software Engineer Department: Engineering Reports To ... Familiarity with formal verification or assurance‑oriented development procedures. * Ability to ...

ADP, Inc.

Senior Software Test Engineer

Melbourne, FL · On-site

$100 - $125/hr

Engineering Manager / QA Lead FLSA Status: Exempt / Full-time Salary Range: $100,000-$140,000 ... Familiarity with formal verification procedures. * Ability to work effectively in a team ...

New

AERONIX INC

Senior Software Test Engineer

Melbourne, FL · On-site

$100K - $140K/yr

Engineering Manager / QA Lead FLSA Status: Exempt / Full-time Salary Range: $100,000-$140,000 ... Familiarity with formal verification procedures. * Ability to work effectively in a team ...

Acara Solutions

Integration/Test Engineer

Palm Bay, FL · On-site

$60/hr

Integration/Test Engineer Location: Palm Bay, FL Employment: Temp to Perm (12 months) Industry ... Knowledge of requirements-based testing and formal verification processes and Fault insertion ...

Govcio LLC

Sr. Systems Engineer- Hybrid Remote

Tampa, FL · On-site

$95K - $130K/yr

... through formal verification methods. Translates high-level product development strategies into ... Provide advanced engineering and architecture ownership across the following specialization:

Govcio LLC

Sr. Systems Engineer- Hybrid Remote

Tampa, FL · On-site +1

$95K - $130K/yr

The PKI Systems Engineer will serve as a primary technical authority for establishing enterprise ... through formal verification methods. Translates high-level product development strategies into ...

Govcio LLC

Sr. Systems Engineer- Hybrid Remote

Tampa, FL · On-site

$95K - $130K/yr

... through formal verification methods. Translates high-level product development strategies into ... Provide advanced engineering and architecture ownership across the following specialization:

Govcio LLC

Sr. Systems Engineer- Hybrid Remote

Tampa, FL · On-site

$95K - $130K/yr

... through formal verification methods. Translates high-level product development strategies into ... Provide advanced engineering and architecture ownership across the following specialization:

Govcio LLC

Sr. Systems Engineer- Hybrid Remote

Tampa, FL · On-site

$95K - $130K/yr

... through formal verification methods. Translates high-level product development strategies into ... Provide advanced engineering and architecture ownership across the following specialization:

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Formal Verification Engineer information

See Florida salary details

$59.8K

$106.6K

$152.1K

How much do formal verification engineer jobs pay per year?

As of Sep 8, 2026, the average yearly pay for formal verification engineer in Florida is $106,578.00, according to ZipRecruiter salary data. Most workers in this role earn between $101,600.00 and $101,600.00 per year, depending on experience, location, and employer.

What is a formal verification engineer?

A Formal Verification Engineer is responsible for ensuring the correctness of hardware or software designs using mathematical and logical techniques. They apply formal methods to verify that a system behaves as intended, identifying potential design flaws early in the development process. This involves writing formal properties, using model checking tools, and collaborating with design and validation teams. Their work helps improve reliability, reduce bugs, and enhance the efficiency of verification compared to traditional simulation-based methods.

What are the common daily responsibilities of a formal verification engineer?

As a Formal Verification Engineer, your typical day involves creating and analyzing formal properties, developing assertions, and using formal verification tools to mathematically prove correctness of hardware designs. You'll collaborate closely with design and simulation teams to review specifications, identify verification requirements, and debug issues found during the verification process. Regular documentation of findings, participation in code and design reviews, and ongoing learning about new verification methodologies are also important parts of the role. This dynamic environment requires both technical depth and proactive teamwork to ensure high-quality design outcomes.

What are the key skills and qualifications needed to thrive as a formal verification engineer?

To thrive as a Formal Verification Engineer, you need a strong background in digital design, computer architecture, and logic, typically supported by a degree in electrical engineering, computer science, or a related field. Expertise in formal verification tools such as Cadence JasperGold, Synopsys VC Formal, or Mentor Questa, along with proficiency in hardware description languages (HDLs) like Verilog or VHDL, is essential. Strong analytical thinking, attention to detail, and effective communication skills help you collaborate with design and verification teams and present complex findings. These competencies are critical for ensuring hardware systems are bug-free, reliable, and meet stringent industry standards.

What are popular job titles related to Formal Verification Engineer jobs in Florida?

For Formal Verification Engineer jobs in Florida, the most frequently searched job titles are:

What job categories do people searching Formal Verification Engineer jobs in Florida look for?

The top searched job categories for Formal Verification Engineer jobs in Florida are:

Formal Verification Engineer jobs near you
Infographic showing various Formal Verification Engineer job openings in Florida as of August 2026, with employment types broken down into 95% Full Time, 2% Part Time, and 3% Contract. Highlights an 86% Physical, 5% Hybrid, and 9% Remote job distribution, with an average salary of $106,578 per year, or $51.2 per hour.

Senior FPGA Design Engineer

AERONIX INC

Melbourne, FL • On-site

$145K - $175K/yr

Full-time

Re-posted 17 days ago

Job description


Job Title: Senior FPGA Engineer
Department: Engineering
Reports To: Functional Team Lead / Program Manager
FLSA Status: Exempt / Full-time

Salary Range:   $145k - $175k Annually

DoD Secret clearance (or higher) REQUIRED.


ROLE

We are seeking a Senior FPGA Design Engineer with at least 10 years of experience to develop the architecture, implementation, and verification of complex, high-speed FPGA solutions. The ideal candidate will have deep expertise in high-bandwidth interfaces such as PCIe Gen4/5, 10 to 100G+ Ethernet, and DDR4/DDR5, along with strong skills in RTL design (VHDL/Verilog/ SystemVerilog), timing closure, and signal integrity. Experience with Cryptography, DSP and RF applications is strong plus. This role involves driving FPGA design from concept through production, integrating vendor IP, optimizing for low latency and high throughput, and performing rigorous verification and lab validation. The engineer will collaborate across hardware and software teams, mentor junior engineers, and ensure designs meet stringent reliability and compliance standards.

RESPONSIBILITIES

  • Lead full life-cycle FPGA development, from requirements and architecture through RTL implementation (Verilog/VHDL), verification, and system integration across multiple FPGA families. 
  • Define and document FPGA architecture, including block diagrams, clocking strategies, and trade-off analyses; participate in and conduct design reviews. 
  • Develop robust, reusable, and self-checking testbenches; implement functional coverage models and achieve code coverage closure. 
  • Create and execute detailed test plans, procedures, and reports; ensure verification rigor and traceability. 
  • Collaborate with hardware and software teams to integrate FPGA designs at the board and system level; support lab bring-up, debug, and qualification testing. 
  • Implement and validate JTAG boundary scan and other DFT features; ensure compliance with design-for-test and reliability standards. 
  • Drive continuous improvement in design practices, coding standards, and verification methodologies; mentor junior engineers and contribute to technical reviews.

REQUIRED SKILLS

  • Strong proficiency in RTL design using Verilog/VHDL, including custom implementations beyond vendor IP integration.
  • Strong experience in testbench development, functional coverage, and verification of complex FPGA designs. 
  • Proficient with FPGA simulation and synthesis tools (e.g., QuestaSim, ModelSim, Riviera-PRO, Xilinx Vivado, Intel Quartus).
  • Proficiency of FPGA architecture and optimization techniques for timing closure, floor-planning, and resource utilization.
  • Ability to perform FPGA power estimation and analysis using vendor tools and optimize designs for power and thermal constraints.
  • Strong understanding of high-speed interfaces (PCIe, Ethernet, Serial RapidIO, DDRx) and control protocols (I²C, SPI, RS-232/422). 
  • Experience with System-on-Chip technologies.

PREFERRED SKILLS

  • Proficiency in FPGA Block Design development and debugging (e.g., Vivado, Libero).
  • Familiarity with Universal Verification Methodology (UVM).
  • Familiarity with Microsemi Libero and Lattus Diamond.
  • Familiarity with revision control systems (Git/Bitbucket) and scripting in Python, TCL, or Linux shell for automation. 
  • Skilled in FPGA lab validation using oscilloscopes, logic analyzers, and protocol analyzers. 
  • Support JTAG Boundary scan design and testing
  • Experience with Cryptography, Digital Signal Processing and RF Applications
  • MATLAB modeling
  • Strong oral and written communication skills, with ability to document and present technical work clearly. 
  • Experience collaborating in Agile environments and using tools like Jira and requirements management systems (e.g., Jama).
  • Familiarity with Manufacturing processes, and Electronic Stress Screening.
  • Understanding of formal verification processes and compliance standards.

QUALIFICATIONS

  • Bachelor’s Degree in Electrical Engineering, Computer Engineering, or related field.
  • Minimum 10 years of relevant experience in FPGA design.
  • Excellent written and verbal communication skills.
  • Ability to work in a collaborative team environment.
  • DoD Secret clearance (or higher) REQUIRED.
  • Position located in Melbourne, FL or Greenville, SC (not remote).