1

Sta Engineer Jobs in Florida (NOW HIRING)

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow ...

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow ...

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow ...

Description As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow ...

FPGA Design Engineer

Melbourne, FL · On-site

$114K - $157K/yr

FPGA Design Engineer Location: Melbourne, FL (Onsite) Duration: 6+ months Start Date: Immediate We ... Static Timing Analysis (STA) * High-Speed Interfaces (PCIe, Ethernet, DDR, SPI, I2C, UART) * FPGA ...

New

Project Engineer Site / Civil Engineering

Tampa, FL · On-site

$72K - $97K/yr

Your Opportunity Stantec's multi-disciplinary office in Tallahassee, Florida has an opportunity for an experienced Project Engineer - Site / Civil Engineering. We are seeking a candidate with ...

Industry/Sector Not Applicable Specialism Data, Analytics & AI Management Level Senior Manager & Summary At PwC, our people in data and analytics engineering focus on leveraging advanced technologies ...

next page

Showing results 1-20

Sta Engineer information

See Florida salary details

$9

$41

$59

How much do sta engineer jobs pay per hour?

As of Jul 13, 2026, the average hourly pay for sta engineer in Florida is $41.05, according to ZipRecruiter salary data. Most workers in this role earn between $35.62 and $51.70 per hour, depending on experience, location, and employer.

What are the key skills and qualifications needed to thrive as a STA Engineer, and why are they important?

To thrive as a STA (Static Timing Analysis) Engineer, you need a strong background in digital circuit design, timing analysis concepts, and a degree in electrical or electronics engineering. Familiarity with EDA tools such as PrimeTime, Tempus, and scripting languages like TCL or Perl is typically required. Excellent problem-solving abilities, attention to detail, and effective communication skills help you collaborate with design teams and address complex timing issues. These skills and qualities are crucial for ensuring reliable chip performance and meeting project deadlines in semiconductor development.

What is the difference between Sta Engineer vs Civil Engineer?

AspectSta EngineerCivil Engineer
Required CredentialsBachelor's in Engineering, PE license often preferredBachelor's in Civil Engineering, PE license common
Work EnvironmentConstruction sites, public infrastructure projectsDesign offices, construction sites, urban planning
Employer & Industry UsagePublic agencies, transportation, utilitiesConstruction firms, consulting, government agencies

Sta Engineers and Civil Engineers share similar credentials and often work in related environments, especially in infrastructure projects. While Sta Engineers focus more on site supervision and project management, Civil Engineers are involved in design and planning. Both roles are essential in construction and public works sectors, with overlapping skills and industry usage.

What are some common challenges faced by a STA Engineer and how can they be addressed?

STA Engineers often encounter challenges such as managing tight project schedules, dealing with complex timing constraints, and collaborating effectively with cross-functional teams including design, verification, and physical implementation engineers. Navigating these complexities requires strong problem-solving skills, attention to detail, and effective communication. Staying current with industry-standard EDA tools and continuous learning about evolving timing methodologies can help address these challenges and ensure successful project outcomes.

What is an STA Engineer?

An STA (Static Timing Analysis) Engineer is a professional who specializes in verifying the timing performance of digital integrated circuits. They use specialized software tools to analyze the timing of signals within a chip, ensuring that all paths meet the required timing constraints for correct operation. STA Engineers work closely with design and verification teams to identify and resolve timing violations, and play a critical role in the chip design process to ensure reliable and high-performance products.
Timing Design Engineer

Timing Design Engineer

Apple

Melbourne, FL • On-site

Full-time

Re-posted 19 days ago


Apple rating

8.1

Company rating: 8.1 out of 10

Based on 670 frontline employees who took The Breakroom Quiz

5th of 30 rated technology retailers


Job description

Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other's ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. It's the diversity of our people and their thinking that inspires the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you'll do more than join something - you'll add something.
Description
As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.
Minimum Qualifications
Bachelors of Science in Electrical Engineering.
Preferred Qualifications
Proven knowledge of the ASIC design timing closure flow and methodology.
2+ years of experience in writing ASIC timing constraints and timing closure.
Expertise in STA tools (Primetime) and flow, knowledge of timing corners/modes, process variations and signal integrity related issues.
Hands on experience in timing/SDC constraints generation and management.
Proficient in scripting languages (Tcl and Perl).
Familiarity with synthesis, DFT and backend related methodology and tools.
Strong communication skills are a pre-requisite - you will be collaborating with many diverse groups at Apple.
The ideal candidate will be a self-starter and highly motivated to be successful at Apple.

What Apple employees say

Pay

Benefits

Hours and flexibility

Workplace

Get the full story on Breakroom


Apple logo

About Apple

Sourced by ZipRecruiter

Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it.

Industry

Computer and electronic product manufacturing

Company size

10,000+ Employees

Headquarters location

Cupertino, CA, US

Year founded

1976