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Flex Remote Design Verification Engineer Jobs (NOW HIRING)

RTL Design/AMS Verification Engineer

Richardson, TX · On-site +1

$122K - $149K/yr

Remote considered based on experience and qualifications We are seeking an experienced RTL Design Engineer with a strong background in RTL design, design verification, synthesis, and physical ...

As a Design Verification Engineer, you will be part of an agile team working with experienced engineers across the industry, focused on developing ASIC solutions for Meta's data center applications.

As a Design Verification Engineer, you will be part of an agile team working with experienced engineers across the industry, focused on developing ASIC solutions for Meta's data center applications.

Role Overview As an ASIC Design Verification Engineer, you will play a critical role in ensuring ... Flexible work environment with remote work options If you are excited about ensuring the highest ...

ASIC Design Verification Engineer

$139K - $169K/yr

... Design Verification processes using the latest methodologies, tools, and industry technologies. Minimum Qualifications: * Bachelor's degree in Computer Science, Computer Engineering, or a related ...

The Role We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the ...

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Flex Remote Design Verification Engineer information

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$105.5K

$149.2K

$167K

How much do flex remote design verification engineer jobs pay per year?

As of Jul 13, 2026, the average yearly pay for flex remote design verification engineer in the United States is $149,150.00, according to ZipRecruiter salary data. Most workers in this role earn between $136,000.00 and $166,000.00 per year, depending on experience, location, and employer.
What are the most commonly searched types of Remote Design Verification Engineer jobs? The most popular types of Remote Design Verification Engineer jobs are:
Infographic showing various Flex Remote Design Verification Engineer job openings in the United States as of July 2026, with employment types broken down into 89% Full Time, 8% Part Time, and 3% Contract. Highlights an 87% Physical, 3% Hybrid, and 10% Remote job distribution, with an average salary of $149,150 per year, or $71.7 per hour.

$139K - $169K/yr

Full-time

Re-posted 20 hours ago


Job description

Role - Design Verification Engineer
Location: Remote (must be aligned with PST time zone / willing to work PST hours)
Contract Term: Contract
Job Description:
We are seeking an ASIC Design Verification Engineer whose role will be to verify the functionality, performance, and robustness of our custom silicon designs. You will help define the verification approach, contribute to methodology, and work closely with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers. This is a hands-on role with high ownership, deep technical engagement, and the opportunity to shape first-generation silicon.
Responsibilities
  • Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
  • Build System Verilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
  • Write System Verilog Assertions (SVA) and integrate formal verification where appropriate.
  • Drive constrained random and directed testing strategies to validate functionality, corner cases, and stress scenarios.
  • Run simulations, triage failures, drive root-cause analysis, and collaborate with RTL designers to resolve issues.
  • Implement and maintain functional coverage, code coverage, assertion coverage, and ensure coverage closure for sign-off.
  • Manage regression testing, simulation farms, and CI pipelines to ensure high test throughput and fast debug iterations.
  • Participate in design reviews and microarchitecture discussions.

Qualifications
  • B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
  • 3+ years of experience in ASIC/SoC verification.
  • Solid understanding of SystemVerilog, digital logic, and hardware verification flows.
  • Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision) and coverage tool.
  • Experience with test planning, testbench development, constrained-random testing, and coverage analysis.
  • Familiarity with a scripting language (e.g. Python, Perl, TCL) and revision control system (e.g. Git).

Nice to Have
  • Experience with UVM-based testbench development, functional coverage, SystemVerilog assertions, and regression management.
  • Familiarity with developing and integrating reference models.
  • Understanding of RTL design flows and some industry standard interfaces (e.g. APB/AHB/AXI).
  • Experience working in cross-functional, geographically distributed teams.
  • Experience in space, telecom, or RF/digital mixed systems is a plus.