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Entry Level Asic Rtl Design Engineer Jobs in Phoenix, AZ

Senior FPGA Engineer

Chandler, AZ · On-site

$106K - $142K/yr

Experience in FGPA or ASIC Design * FPGA Implementation * Xilinx * RTL Simulations * Bachelors in Electrical Engineer/Computer Engineering (or related degree) #J-18808-Ljbffr

New

Collaborate closely with process integration, test, packaging, and ASIC teams to ensure design ... MS or PhD in Mechanical Engineering, Electrical Engineering, Physics, Materials Science, or related ...

R-10064841As a DfT engineer, you will join a highly experienced team. Your key responsibilities ... Master's degree (MSEE) with majority of courses relevant to Digital Design, RTL coding, DfT ...

FPGA Engineer (Space)

Tempe, AZ · On-site

$129K - $194K/yr

What you'll do As a FPGA Engineer on the Space Infrastructure team, you will design, implement, and ... Contribute to architecture, design, and implementation of FPGA based digital systems * Develop RTL ...

FPGA Design Engineer II

Phoenix, AZ

$121K - $167K/yr

As an FPGA Design Engineer II you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques

FPGA Design Engineer II

Phoenix, AZ

$118K - $163K/yr

As an FPGA Design Engineer II you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques

FPGA Design Engineer II

Phoenix, AZ

$116K - $160K/yr

As an FPGA Design Engineer II you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques

FPGA Design Engineer II

Phoenix, AZ

$116K - $160K/yr

As an FPGA Design Engineer II you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques

FPGA Design Engineer II

Phoenix, AZ

$114K - $157K/yr

As an FPGA Design Engineer II you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques

FPGA Design Engineer II

Phoenix, AZ

$121K - $168K/yr

As an FPGA Design Engineer II you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques

FPGA Design Engineer II

Phoenix, AZ

$122K - $168K/yr

As an FPGA Design Engineer II you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques

FPGA Design Engineer II

Phoenix, AZ

$122K - $168K/yr

As an FPGA Design Engineer II you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques

FPGA Design Engineer II

Phoenix, AZ

$121K - $167K/yr

As an FPGA Design Engineer II you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques

FPGA Design Engineer II

Phoenix, AZ

$117K - $161K/yr

As an FPGA Design Engineer II you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques

FPGA Design Engineer II

Phoenix, AZ

$122K - $168K/yr

As an FPGA Design Engineer II you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques

FPGA Design Engineer II

Tempe, AZ

$119K - $164K/yr

As an FPGA Design Engineer II you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques

FPGA Design Engineer II

Phoenix, AZ

$118K - $163K/yr

As an FPGA Design Engineer II you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques

FPGA Design Engineer II

Phoenix, AZ

$120K - $165K/yr

As an FPGA Design Engineer II you will develop FPGA designs for all major vendors and device ... FPGA/ASIC design experience in one or more of the following areas: * Radar processing techniques

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Entry Level Asic Rtl Design Engineer information

See Phoenix, AZ salary details

$93.3K

$149.1K

$200.6K

How much do entry level asic rtl design engineer jobs pay per year?

As of Sep 14, 2026, the average yearly pay for entry level asic rtl design engineer in Phoenix, AZ is $149,131.00, according to ZipRecruiter salary data. Most workers in this role earn between $130,600.00 and $178,700.00 per year, depending on experience, location, and employer.

What does an entry level ASIC RTL design engineer do?

An Entry Level ASIC RTL (Register Transfer Level) Design Engineer is responsible for designing and developing the digital logic that forms the core of Application Specific Integrated Circuits (ASICs). They use hardware description languages like Verilog or VHDL to create and simulate circuit designs based on functional specifications. Their tasks often include coding, debugging, verification, and collaborating with senior engineers to ensure the design meets performance, power, and area requirements. This role is essential for bringing complex digital systems from concept to physical implementation in products such as processors, networking chips, and other specialized electronics.

What are the key skills and qualifications needed to thrive as an entry level ASIC RTL design engineer?

To thrive as an Entry Level ASIC RTL Design Engineer, you need a solid background in digital logic design, computer architecture, and proficiency in hardware description languages like Verilog or VHDL, typically supported by a degree in electrical or computer engineering. Familiarity with EDA tools such as Synopsys or Cadence, and understanding of simulation, synthesis, and verification flows are commonly required. Strong problem-solving abilities, attention to detail, and effective teamwork and communication skills help individuals excel in this role. These skills enable accurate and efficient hardware design, seamless integration with larger teams, and successful delivery of complex semiconductor products.

What are some typical challenges faced by entry level ASIC RTL design engineers in their first year, and how can they overcome them?

Entry Level ASIC RTL Design Engineers often encounter challenges such as understanding complex design specifications, learning company-specific design flows and tools, and debugging RTL code efficiently. Collaborating closely with senior engineers and participating in code reviews can accelerate learning and help address these challenges. Additionally, taking initiative to study relevant documentation and seeking feedback regularly will help new engineers build confidence and technical competence in their role.

What is the difference between Entry Level Asic Rtl Design Engineer vs Digital Design Engineer?

AspectEntry Level Asic Rtl Design EngineerDigital Design Engineer
Required CredentialsBachelor's in Electrical Engineering or Computer Engineering; knowledge of HDL (Verilog/VHDL)Bachelor's in Electrical Engineering, Computer Engineering, or related; HDL knowledge often required
Work EnvironmentSemiconductor companies, chip design teams, hardware development labsElectronics companies, integrated circuit design teams, hardware development labs
Industry UsagePrimarily in ASIC/FPGA chip designIn digital hardware design across various sectors including consumer electronics and telecom

While both roles involve digital hardware design and HDL skills, the Entry Level Asic Rtl Design Engineer focuses specifically on ASIC chip development, whereas the Digital Design Engineer may work on a broader range of digital systems, including FPGA and other digital hardware projects.

What are the most commonly searched types of Asic Rtl Design Engineer jobs in Phoenix, AZ?

The most popular types of Asic Rtl Design Engineer jobs in Phoenix, AZ are:

Infographic showing various Entry Level Asic Rtl Design Engineer job openings in Phoenix, AZ as of September 2026, with employment types broken down into 92% Full Time, and 8% Part Time. Highlights an 100% In-person job distribution, with an average salary of $149,131 per year, or $71.7 per hour.

Senior FPGA Engineer

Chandler, AZ • On-site

$106K - $142K/yr

Other

Posted yesterday

New


Job description

Senior FPGA Engineer | Chandler (AZ) | Up to $170,000

Join a growing communications business in Arizona, who build secure communications systems for emergency services, law enforcement and public safety. They provide these capabilities through satellite and space-based communications.


As a Senior FPGA Engineer, you’ll join a small team to work end-to-end on complex FPGAs that are used for satellite communications systems.


This is an on-site position in Chandler. Due to government related work, you must be a US citizen or Green Card holder to be considered for the position.


Skills/Technologies

  • Experience in FGPA or ASIC Design

  • FPGA Implementation

  • Xilinx

  • RTL Simulations

  • Bachelors in Electrical Engineer/Computer Engineering (or related degree)

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