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Engineering Design Manager Jobs in Mountain View, CA

Flux

Aviation Design Engineer/Manager

San Francisco, CA · On-site

$130K/yr

Overview We are seeking an Aviation Design Engineer/Manager to join one of our clients in San ... Plans and reviews the production of engineering drawings and specifications with an expertise in ...

Airswift

Electrical Design Manager

Fremont, CA · On-site

$134K - $172K/yr

The ideal candidate will have a strong electrical engineering background and proven experience leading design initiatives within complex projects. Key Responsibilities: * Lead and manage electrical ...

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All JobsEngineering Design JobsEngineering Design Manager JobsEngineering Design Manager Jobs in Mountain View, CA

Engineering Design Manager information

See Mountain View, CA salary details

$61.9K

$158.6K

$244.8K

How much do engineering design manager jobs pay per year?

As of Sep 5, 2026, the average yearly pay for engineering design manager in Mountain View, CA is $158,627.00, according to ZipRecruiter salary data. Most workers in this role earn between $128,600.00 and $177,000.00 per year, depending on experience, location, and employer.

What does an engineering design manager do?

An Engineering Design Manager oversees the design process for engineering projects, coordinating teams of engineers and designers to ensure that project goals are met efficiently and effectively. They are responsible for planning, organizing, and reviewing design work, ensuring compliance with industry standards and client requirements. Additionally, they often liaise with clients, stakeholders, and other departments to align the design vision with project specifications and timelines. Their leadership is crucial in solving technical challenges and delivering innovative solutions within budget.

What does an engineering design manager do?

The job duties of an engineering design manager include overseeing a team of engineers and CAD designers on engineering projects. In addition to providing leadership to staff, in this career, you manage the budget planning for each project, work with concept development, and ensure that plans meet company or client needs and engineering standards. You offer guidance throughout the design process and inspect and sign off on design plans to ensure that they meet quality standards. As a manager, you are also responsible for providing effective staffing strategies and workflow.

What are the main challenges an engineering design manager faces when balancing project deadlines with innovation?

Engineering Design Managers often need to ensure that their teams deliver high-quality designs within tight project timelines while also encouraging creativity and innovation. One of the main challenges is managing stakeholder expectations and resource constraints, as pushing for innovative solutions can sometimes require more time and iterative testing. Effective communication, prioritization, and fostering a collaborative environment help address these challenges, ensuring that projects remain on schedule without stifling new ideas. Managers frequently coordinate between engineering teams, clients, and other departments to align goals and keep projects moving forward.

What is the difference between Engineering Design Manager vs Mechanical Engineer?

AspectEngineering Design ManagerMechanical Engineer
Required CredentialsBachelor's or Master's in Engineering, often with management certificationsBachelor's or Master's in Mechanical Engineering
Work EnvironmentLeads design teams, oversees projects, collaborates with cross-functional departmentsDesigns, analyzes, and tests mechanical systems, often working in labs or on-site
Employer & Industry UsageUsed in manufacturing, aerospace, automotive, and engineering firms for leadership rolesCommon in product design, manufacturing, and R&D sectors

The Engineering Design Manager focuses on leading design teams and managing projects, requiring leadership skills and project management experience. In contrast, Mechanical Engineers are involved in the technical design and analysis of mechanical systems. Both roles often require similar engineering credentials but differ in scope and responsibilities.

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Engineering Design Manager jobs near you
Infographic showing various Engineering Design Manager job openings in Mountain View, CA as of June 2026, with employment types broken down into 90% Full Time, 9% Part Time, and 1% Contract. Highlights an 90% Physical, 3% Hybrid, and 7% Remote job distribution, with an average salary of $158,627 per year, or $76.3 per hour.

Manager, Package Design Engineering

Astera Labs

San Jose, CA • On-site

Full-time

Re-posted 12 days ago

Job description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.
Role Overview
Astera Labs is seeking a Manager, Package Design Engineering to lead and scale our Package Design team in San Jose. In this high-impact role, you'll own the end-to-end delivery of advanced IC packaging solutions-from early architecture definition through production ramp-enabling the next generation of AI infrastructure and connectivity products.
As the semiconductor industry races toward chiplet-based architectures, 2.5D/3D integration, and ever-increasing bandwidth demands, packaging has become a critical differentiator. You'll build and mentor a high-performing team while driving cross-functional execution with silicon architecture, SIPI, PCB, validation, manufacturing, and external partners including substrate vendors and OSATs. Your work will directly impact Astera Labs' ability to deliver industry-leading PCIe, CXL, and Ethernet connectivity solutions to the world's most demanding hyperscale and AI customers.
This role offers the opportunity to shape design methodology, establish scalable standards, and enable chip-package-board co-design frameworks across multiple product lines in a fast-moving, innovation-driven environment.
Key Responsibilities
  • Team Leadership & Execution
    • Build, mentor, and scale a high-performing package design engineering team with clear ownership, accountability, and execution flows
    • Establish design templates, standards, and best-known methods (BKMs) across multiple concurrent programs
    • Lead design reviews, audits, and issue resolution through bring-up and production ramp
  • Package Design Delivery
    • Own end-to-end package design execution including FCBGA/FCCSP, monolithic, multi-die, and chiplet-based designs from concept feasibility through tape-out and production
    • Define and review substrate stack-ups, pad stacks, routing strategies, and design constraints to meet electrical, thermal, mechanical, and manufacturability requirements
    • Drive technical tradeoffs across performance, cost, yield, and schedule, ensuring high-quality design closure and on-time delivery
  • Cross-Functional Collaboration
    • Partner with SIPI, silicon architecture, system/board design, and product teams to drive chip-package-board co-design and resolve system-level challenges
    • Collaborate with OSATs and substrate vendors to ensure design feasibility, manufacturability, and alignment with evolving design rules and technology roadmaps
    • Support adoption of advanced packaging technologies such as 2.5D, chiplet, CPO/CPC, and heterogeneous integration platforms
  • Methodology & Automation
    • Develop and scale design methodologies and automation flows to improve efficiency, quality, and repeatability across the organization

Basic Qualifications
  • Bachelor's degree in Electrical Engineering, Materials Science, or related field
  • 10+ years of progressive experience in IC package design using tools such as Cadence Allegro APD/SiP
  • 5+ years of leadership experience managing teams or technical organizations in IC packaging environments
  • Strong hands-on expertise in end-to-end package design with proven delivery of HVM-ready FCBGA/FCCSP packages using Cadence APD tool
  • Experience with high-speed SerDes systems (PCIe Gen5/6/7, CXL, Ethernet 100G/200G/400G+) and advanced nodes (7nm, 5nm, 3nm)
  • Deep understanding of substrate technologies, stack-ups, routing constraints, assembly processes, and SI/PI fundamentals
  • Proven experience working with OSATs and substrate vendors through development and production ramp
  • Experience working with OSATs and substrate vendors through development and production ramp
  • Experience with advanced packaging architectures such as 2.5D/3D, chiplet, or heterogeneous integration

Preferred Qualifications
  • Master's degree in Electrical Engineering or related field
  • Experience with advanced packaging architectures such as 2.5D/3D, chiplet, or heterogeneous integration
  • Experience implementing automation, scripting (Python, SKILL, Tcl), or workflow optimization
  • Background in early package feasibility, platform evaluation, and technology roadmap development
  • Familiarity with chip floor planning, architecture, and system-level tradeoffs
  • Exposure to SIPI modeling and analysis, thermal, and mechanical performance considerations

The base salary range is $230,000 USD - $265,000 USD. This position can be hired as a Manager Level or Director Level. Your base salary will be determined based on location, experience, and employees' pay in similar positions.
We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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