Eda Jobs in Oregon (NOW HIRING)

Job Details

Job Details: Job Description: As a Design Administrator (DA), you will be responsible for enabling and supporting the engineering infrastructure, design environments, and automation frameworks used in the development of Intel's technology vehicles and test chips. You will serve as a key technical resource for engineering teams by maintaining EDA environments, deploying workflow enhancements, automating repetitive processes, and ensuring engineers can efficiently execute their daily design activities. This role requires a combination of software development, DevOps, EDA tool administration, and customer support skills. You will work closely with design engineers, CAD teams, infrastructure partners, and tool vendors to improve engineering productivity, drive workflow modernization, and implement scalable solutions that improve the overall user experience. Your contributions will directly impact engineering efficiency by reducing manual effort, streamlining environment deployment, improving tool reliability, and enabling adoption of modern software development and AI-driven workflows.

Business Group

This position is part of Intel's Design Enablement (DE) organization, which provides design and manufacturing services to internal and external customers. Within DE, the Lead Vehicle Development (LVD) organization develops test chips, validation vehicles, and design infrastructure solutions that enable process technology development and product innovation. The Test Chip Engineering(TCE) team is responsible for delivering and supporting engineering environments, EDA infrastructure, automation frameworks, parametric layout synthesis tools and development workflows that enable successful execution of design and technology development programs across multiple projects.

Key Responsibilities

• Administer and support engineering design environments used for layout, verification, and technology development activities.
• Develop and maintain automation solutions, scripts, and utilities to improve engineering productivity and reduce manual effort.
• Deploy, configure, and support EDA tools and environments, including Cadence Virtuoso, Calibre, IC Validator (ICV), and related infrastructure.
• Manage and support GitHub repositories, version control systems, branching strategies, code release processes, and development workflows.
• Develop and maintain DevOps and CI/CD solutions used to automate engineering and software deployment processes.
• Create and support engineering setup frameworks, environment wrappers, runset enablement methodologies, and workflow automation solutions.
• Troubleshoot and resolve user issues related to EDA tools, engineering environments, infrastructure, access management, and workflow execution.
• Partner with engineering teams to gather requirements, identify pain points, and drive continuous workflow improvements and new feature deployments.
• Support engineering database management, library administration, access control processes, and environment configuration activities.
• Evaluate and deploy AI-enabled solutions that improve engineering productivity, automation capabilities, and user experience.
• Collaborate with infrastructure teams, CAD teams, and external vendors to resolve technical issues and implement enhancements.
• Develop technical documentation, user guides, and best-known methods (BKMs) to improve user onboarding and self-service capabilities.
• Support a large engineering user community by providing timely issue resolution, consultation, and technical guidance.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a STEM related technical discipline. (Bachelor's and 5+ years of experience -OR- Masters and 2+ years of experience -OR- PhD and 1+ years of experience).
• 2+ years of hands-on experience with EDA tools such as Cadence Virtuoso, Calibre, IC Validator (ICV), and related physical design and verification tools.
• 2+ years of experience in software development and scripting using Python, Shell, TCL, Perl, or similar programming languages.
• Experience with GitHub, Git, version control systems, and collaborative software development workflows.
• Hands-on experience with debugging and managing VLSI layouts, debugging DRC/LVS flows.
• Experience working in Linux/Unix environments.
• Experience in troubleshooting, debugging, and problem-solving.

Preferred Qualifications

• Experience supporting Design Automation, CAD, or semiconductor design environments.
• Experience with DevOps, CI/CD frameworks, infrastructure automation, and software deployment methodologies.
• Familiarity with engineering database management, library administration, access control systems, and design workflows.
• Experience driving migration efforts involving modern development platforms, source control systems, and workflow modernization.
• Experience utilizing AI tools to improve software development, automation, and engineering productivity.
• Demonstrated ability to lead cross-functional infrastructure and automation improvement initiatives.

Job Type

Experienced Hire

Shift

Shift 1 (United States of America)

Primary Location

US, Oregon, Hillsboro

Benefits

• Competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation.

Annual Salary Range

Annual Salary Range for jobs which could be performed in the US: $128,880.00-245,160.00 USD The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Future Opportunity

This is your opportunity to shape the future of semiconductor technology and become part of the journey.