1

Drc Testing Jobs in California (NOW HIRING)

next page

Showing results 1-20

Drc Testing information

See California salary details

$9

$20

$26

How much do drc testing jobs pay per hour?

As of Aug 18, 2026, the average hourly pay for drc testing in California is $20.10, according to ZipRecruiter salary data. Most workers in this role earn between $17.07 and $21.59 per hour, depending on experience, location, and employer.

What is a DRC Testing?

A DRC (Design Rule Checking) Testing job involves verifying semiconductor chip layouts to ensure they meet manufacturing and design requirements. Engineers use specialized EDA (Electronic Design Automation) tools to detect and fix rule violations related to spacing, width, and other constraints. This role is essential in the chip design flow to prevent fabrication errors and optimize performance. DRC testers work closely with design and verification teams to improve layout quality and ensure compliance with industry standards.

What does a DRC Testing professional do?

Professionals in DRC Testing are responsible for designing and executing test cases, documenting results, and reporting defects using issue tracking systems. Their work often involves collaborating closely with development teams to troubleshoot and resolve problems, as well as verifying that fixes meet project requirements. Regular duties may also include maintaining test documentation, participating in team meetings, and contributing to continuous process improvement. By ensuring comprehensive testing and clear communication, they play a critical role in the successful deployment of software products.

What are the key skills and qualifications needed for DRC Testing?

To thrive in DRC Testing, candidates need a solid understanding of software testing methodologies, quality assurance processes, and a relevant background in computer science or engineering. Familiarity with testing tools such as Selenium, JIRA, or TestRail, and relevant certifications like ISTQB are often expected. Attention to detail, analytical thinking, and strong communication skills help individuals excel in diagnosing and reporting issues. These skills ensure effective identification and resolution of defects, contributing to the delivery of reliable, high-quality digital solutions.

What are the most commonly searched types of Drc Testing jobs in California?

The most popular types of Drc Testing jobs in California are:

What job categories do people searching Drc Testing jobs in California look for?

The top searched job categories for Drc Testing jobs in California are:

Infographic showing various Drc Testing job openings in California as of August 2026, with employment types broken down into 1% As Needed, 88% Full Time, 8% Part Time, 2% Contract, and 1% Nights. Highlights an 87% Physical, 3% Hybrid, and 10% Remote job distribution, with an average salary of $41,816 per year, or $20.1 per hour.

dft engineer - 1293079

Ethan Alexander Group

Irvine, CA

Full-time

Re-posted 28 days ago


Job description

DFT Engineer


Responsibilities

  • Define & document DFT requirements/Specifications for IP/Block and Chip level
  • Execute DFT Lint to identify scan DRC violations and resolution
  • Top level and hard macro block level scan insertion with high EDT compression ratio (Hybrid LBIST, EDT IP/ATPG, LPCT EDT, AC scan verification with high speed PLL, MBIST, and IJTAG)
  • Plan and Insert MBIST and memory repair (BISR) at RTL
  • Generate and port IJTAG ICL/PDL and STIL patterns for MBIST, ATPG, and JTAG tests
  • ATPG pattern verification on pre/post-route gate-level netlist including 0-delay and SDF
  • Work with backend team for the MBIST/Scan mode constraints generation, scan reorder, VCDs for IR drop analysis during DFT, ECO changes and formal verification (LEC), and timing closure
  • Support test engineer for pattern generation, tester debug and failure analysis.
  • Work with Test Engineering team during Silicon bring-up and creating flow/scripts necessary for debugging/diagnosing compression LPC ATPG patterns (stuck-at/at speed), MBIST patterns on ATE for development and production programs
  • Expert knowledge of Mentor Tessent toolchain

Job Requirements

  • Hands-on hierarchical DFT flow experience from RTL to netlist
  • Strong knowledge and experience with both JTAG (IEEE1149.1) and IJTAG (1687)
  • Experience in inserting EDT, wrapper cells and OCC
  • Experience in analyzing DFT DRC violations and fault coverage analysis
  • Expertise in ATPG. Debug and resolve ATPG DRC and chain trace issues
  • Gate level simulations and debug; both 0-delay and with SDF DFT
  • Expertise in using Cadence for scan stitching and Mentor Tessent tool suite for DFT implementation
  • Experience in debugging tester/ATE failures, silicon bring-up and yield and test time improvement
  • Experience in Perl/TCL scripting and good verbal/written communication skills
  • 7+ years of proven DFT execution experience on mixed-signal SoC with first-pass silicon success