Execute DFT Lint to identify scan DRC violations and resolution * Top level and hard macro block ... Support test engineer for pattern generation, tester debug and failure analysis. * Work with Test ...
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Execute DFT Lint to identify scan DRC violations and resolution * Top level and hard macro block ... Support test engineer for pattern generation, tester debug and failure analysis. * Work with Test ...
Quick apply
Execute DFT Lint to identify scan DRC violations and resolution * Top level and hard macro block ... Support test engineer for pattern generation, tester debug and failure analysis. * Work with Test ...
San Diego, CA · On-site
$144K - $148K/yr
Support physical verification including DRC, LVS, and antenna checks. * Work closely with backend ... Develop and maintain automation scripts for verification flows, reporting, and regression testing.
San Diego, CA · On-site
$144K - $148K/yr
Support physical verification including DRC, LVS, and antenna checks. * Work closely with backend ... Develop and maintain automation scripts for verification flows, reporting, and regression testing.
Proficiency with SPICE simulation tools (HSPICE, PSPICE, Spectre), LVS/DRC verification tools, and ... Deep understanding of defect physics, testing/probing structures, and their impact on defect ...
Proficiency with SPICE simulation tools (HSPICE, PSPICE, Spectre), LVS/DRC verification tools, and ... Deep understanding of defect physics, testing/probing structures, and their impact on defect ...
Proficiency with SPICE simulation tools (HSPICE, PSPICE, Spectre), LVS/DRC verification tools, and ... Deep understanding of defect physics, testing/probing structures, and their impact on defect ...
Proficiency with SPICE simulation tools (HSPICE, PSPICE, Spectre), LVS/DRC verification tools, and ... Deep understanding of defect physics, testing/probing structures, and their impact on defect ...
Proficiency with SPICE simulation tools (HSPICE, PSPICE, Spectre), LVS/DRC verification tools, and DFT/ATPG methodologies for packaging and advanced nodes. Programming or scripting skills (Python ...
Proficiency with SPICE simulation tools (HSPICE, PSPICE, Spectre), LVS/DRC verification tools, and DFT/ATPG methodologies for packaging and advanced nodes. Programming or scripting skills (Python ...
$120K - $180K/yr
We deliver comprehensive solutions that streamline semiconductor testing, empowering faster time-to ... Schematic) and DRC (Design Rule Checking) to ensure compliance with process design rules
$120K - $180K/yr
We deliver comprehensive solutions that streamline semiconductor testing, empowering faster time-to ... Schematic) and DRC (Design Rule Checking) to ensure compliance with process design rules
San Diego, CA · On-site
$120K - $180K/yr
We deliver comprehensive solutions that streamline semiconductor testing, empowering faster time-to ... Schematic) and DRC (Design Rule Checking) to ensure compliance with process design rules
Quick apply
San Diego, CA · On-site
$120K - $180K/yr
We deliver comprehensive solutions that streamline semiconductor testing, empowering faster time-to ... Schematic) and DRC (Design Rule Checking) to ensure compliance with process design rules
San Diego, CA · On-site
$120K - $180K/yr
We deliver comprehensive solutions that streamline semiconductor testing, empowering faster time-to ... Schematic) and DRC (Design Rule Checking) to ensure compliance with process design rules
San Diego, CA · On-site
$120K - $180K/yr
We deliver comprehensive solutions that streamline semiconductor testing, empowering faster time-to ... Schematic) and DRC (Design Rule Checking) to ensure compliance with process design rules
Sunnyvale, CA · On-site
$230K - $280K/yr
... and testing to bring photonic designs from concept to production-ready silicon. Location San ... Full tape-out ownership: concept → simulation → layout → DRC clean → tapeout → wafer ...
Sunnyvale, CA · On-site
$230K - $280K/yr
... and testing to bring photonic designs from concept to production-ready silicon. Location San ... Full tape-out ownership: concept → simulation → layout → DRC clean → tapeout → wafer ...
$210K - $355K/yr
Provide post-silicon testing and validation support * Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools * Integration ...
$210K - $355K/yr
Provide post-silicon testing and validation support * Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools * Integration ...
$200K - $335K/yr
Provide post-silicon testing and validation support * Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools * Integration ...
$200K - $335K/yr
Provide post-silicon testing and validation support * Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools * Integration ...
Santa Clara, CA · On-site
DFT fundamentals (controllability, observability, scan testing) * Digital design and RTL concepts ... DRC debug and fault model validation * Generating test timing and PnR collaterals * Expertise in ...
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Santa Clara, CA · On-site
DFT fundamentals (controllability, observability, scan testing) * Digital design and RTL concepts ... DRC debug and fault model validation * Generating test timing and PnR collaterals * Expertise in ...
Santa Clara, CA · On-site
... and scan-based testing * Proven expertise in ATPG pattern generation, analysis, and debug ... DRC debug * Coverage Analysis * Pattern Generation for different fault models Qualification: BE ...
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Santa Clara, CA · On-site
... and scan-based testing * Proven expertise in ATPG pattern generation, analysis, and debug ... DRC debug * Coverage Analysis * Pattern Generation for different fault models Qualification: BE ...
Santa Clara, CA · On-site
DFT fundamentals (controllability, observability, scan testing) * Digital design and RTL concepts ... DRC debug and fault model validation * Generating test timing and PnR collaterals * Expertise in ...
Quick apply
Santa Clara, CA · On-site
DFT fundamentals (controllability, observability, scan testing) * Digital design and RTL concepts ... DRC debug and fault model validation * Generating test timing and PnR collaterals * Expertise in ...
Manage DRC, fab outputs (Gerbers, assembly drawings), vendor coordination; maintain schematic ... Execute host interop testing, standards compliance (IEEE 802.3, CMIS, OIF), and reliability ...
Manage DRC, fab outputs (Gerbers, assembly drawings), vendor coordination; maintain schematic ... Execute host interop testing, standards compliance (IEEE 802.3, CMIS, OIF), and reliability ...
Execute DFT verification, debug, and DFT DRC closure using Siemens Tessent * Identify, debug, and ... Tester pattern conversion * Silicon characterization * Exposure to mixed-signal or SERDES DFT ...
Execute DFT verification, debug, and DFT DRC closure using Siemens Tessent * Identify, debug, and ... Tester pattern conversion * Silicon characterization * Exposure to mixed-signal or SERDES DFT ...
Santa Clara, CA · On-site
Execute DFT verification, debug, and DFT DRC closure using Siemens Tessent * Identify, debug, and ... Tester pattern conversion * Silicon characterization * Exposure to mixed-signal or SERDES DFT ...
Santa Clara, CA · On-site
Execute DFT verification, debug, and DFT DRC closure using Siemens Tessent * Identify, debug, and ... Tester pattern conversion * Silicon characterization * Exposure to mixed-signal or SERDES DFT ...
Irvine, CA · On-site
$200K - $335K/yr
Provide post-silicon testing and validation support * Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools * Integration ...
Irvine, CA · On-site
$200K - $335K/yr
Provide post-silicon testing and validation support * Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools * Integration ...
Sunnyvale, CA · On-site
$210K - $355K/yr
Provide post-silicon testing and validation support * Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools * Integration ...
Sunnyvale, CA · On-site
$210K - $355K/yr
Provide post-silicon testing and validation support * Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools * Integration ...
Irvine, CA · On-site
$200K - $335K/yr
Provide post-silicon testing and validation support * Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools * Integration ...
Irvine, CA · On-site
$200K - $335K/yr
Provide post-silicon testing and validation support * Responsible for evaluating design readiness for scan insertion through RTL and physical design Scan Design Rule Check (DRC) tools * Integration ...
$9.96 - $11.50
0% of jobs
$11.50 - $13.03
1% of jobs
$13.03 - $14.56
5% of jobs
$14.56 - $16.09
11% of jobs
$16.85 is the 25th percentile. Wages below this are outliers.
$16.09 - $17.62
16% of jobs
The median wage is $19.06 / hr.
$17.62 - $19.15
18% of jobs
$19.15 - $20.68
21% of jobs
$21.03 is the 75th percentile. Wages above this are outliers.
$20.68 - $22.21
12% of jobs
$22.21 - $23.74
4% of jobs
$23.74 - $25.28
3% of jobs
$25.28 - $26.81
9% of jobs
$9
$20
$26
A DRC (Design Rule Checking) Testing job involves verifying semiconductor chip layouts to ensure they meet manufacturing and design requirements. Engineers use specialized EDA (Electronic Design Automation) tools to detect and fix rule violations related to spacing, width, and other constraints. This role is essential in the chip design flow to prevent fabrication errors and optimize performance. DRC testers work closely with design and verification teams to improve layout quality and ensure compliance with industry standards.
To thrive in DRC Testing, candidates need a solid understanding of software testing methodologies, quality assurance processes, and a relevant background in computer science or engineering. Familiarity with testing tools such as Selenium, JIRA, or TestRail, and relevant certifications like ISTQB are often expected. Attention to detail, analytical thinking, and strong communication skills help individuals excel in diagnosing and reporting issues. These skills ensure effective identification and resolution of defects, contributing to the delivery of reliable, high-quality digital solutions.
Professionals in DRC Testing are responsible for designing and executing test cases, documenting results, and reporting defects using issue tracking systems. Their work often involves collaborating closely with development teams to troubleshoot and resolve problems, as well as verifying that fixes meet project requirements. Regular duties may also include maintaining test documentation, participating in team meetings, and contributing to continuous process improvement. By ensuring comprehensive testing and clear communication, they play a critical role in the successful deployment of software products.

DFT Engineer
Responsibilities
Job Requirements
Sourced by ZipRecruiter
Recruiting and staffing services
1 - 10 Employees
Mission Hills, CA, US
2013